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Adventurer
Adventurer
1,641 Views
Registered: ‎09-30-2015

Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

I have a project which targets a xc7z030 that generates a bit file.  I am trying to fit the design in an xc7z012, but I get the following error at bitgen:

  • [DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i.

I also see this message as a critical warning during implementation:

  • [Route 35-54] Net: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i is not completely routed.

Looking at AR #66314 https://www.xilinx.com/support/answers/66314.html   I don't think this is a congestion error.  Utilization Post-Implementation is as follows:

LUT  22%

LUTRAM 1%

BRAM 21%

DSP 14%

GT 25%

BUFG 19%

PLL 33%

 

The results of report_design_analysis and

report_design_analysis -congestion -complexity -hierarchical_depth 10 are in the attached files

The jpg is a screen grab of the device showing the partially routed net

note: -force_replication_on_nets is set for phys_opt_design

 

Any thoughts on what is preventing the tool from routing the net?

Thanks,

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9 Replies
Xilinx Employee
Xilinx Employee
1,617 Views
Registered: ‎05-08-2012

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Hi @creedxlnx.

If you open the routed design with the routing error, and try to route the net again (route_design -nets [get_nets <name>]), is there more messaging available? This usually prints more messaging for unroutable connections. I suspect an unroutable connection with GT connectivity, since there are many dedicated connections for the CHANNEL and COMMON primitives. Knowing the pin to pin connectivity would help determine what can be done.

 
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Adventurer
Adventurer
1,565 Views
Registered: ‎09-30-2015

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

I'm going to take a look at this now, but I wanted to post the results of trying to route the net and the pin to get another pair of eyes on this.

Nets with Routing Errors:
  ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i
    Unrouted Pin: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_block_i/jesd204_gtx_phy_2_gt/inst/jesd204_gtx_phy_2_gt_i/gt0_jesd204_gtx_phy_2_gt_i/gtpe2_i/PLL1CLK

route_design -nets [get_nets ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i]
Command: route_design -nets [get_nets ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i]
Attempting to get a license for feature 'Implementation' and/or device 'xc7z012s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z012s'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC PDCN-2721] IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 u_pll/inst/clkin1_ibufg drives PLLE2_ADV u_pll/inst/plle2_adv_inst in a different clock region and must do so using local routing resources which may negatively affect clock performance. Use CLOCK_DEDICATED_ROUTE set to FALSE to indicate this is intended.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Interactive Router Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 11771e6c5

Time (s): cpu = 00:00:25 ; elapsed = 00:00:18 . Memory (MB): peak = 2295.172 ; gain = 144.949
INFO: [Route 35-47] Routing for 1 net will be attempted.
Post Restoration Checksum: NetGraph: eeb31cc3 NumContArr: 62027212 Constraints: 0 Timing: 0

Phase 2 Router Initialization
Phase 2 Router Initialization | Checksum: 1da5b4e5f

Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 2304.730 ; gain = 154.508
 Number of Nodes with overlaps = 0
CRITICAL WARNING: [Route 35-276] Interactive router failed to route 1  net.
Resolution: Run report_route_status and review the logfile to identify routing failures.

Unroutable connection Types:
----------------------------
Type 1 : GTPE2_COMMON.PLL0OUTCLK->GTPE2_CHANNEL.PLL1CLK
-----Num Open nets: 1
-----Representative Net: Net[922] ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i
-----GTPE2_COMMON_X0Y0.PLL0OUTCLK -> GTPE2_CHANNEL_X0Y3.PLL1CLK
-----Driver Term: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/gtpe2_common_i/PLL0OUTCLK Load Term [5973]: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_block_i/jesd204_gtx_phy_2_gt/inst/jesd204_gtx_phy_2_gt_i/gt0_jesd204_gtx_phy_2_gt_i/gtpe2_i/PLL1CLK
Ending Interactive Router Task | Checksum: 1da5b4e5f

Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 2307.391 ; gain = 157.168
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 1 Warnings, 1 Critical Warnings and 0 Errors encountered.
route_design failed
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:21 . Memory (MB): peak = 2307.391 ; gain = 157.168
route_design -nets [get_pins ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_block_i/jesd204_gtx_phy_2_gt/inst/jesd204_gtx_phy_2_gt_i/gt0_jesd204_gtx_phy_2_gt_i/gtpe2_i/PLL1CLK]
Command: route_design -nets [get_pins ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_block_i/jesd204_gtx_phy_2_gt/inst/jesd204_gtx_phy_2_gt_i/gt0_jesd204_gtx_phy_2_gt_i/gtpe2_i/PLL1CLK]
Attempting to get a license for feature 'Implementation' and/or device 'xc7z012s'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z012s'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC PDCN-2721] IBUFDS_GT_loads_clock_region: IBUFDS_GTE2 u_pll/inst/clkin1_ibufg drives PLLE2_ADV u_pll/inst/plle2_adv_inst in a different clock region and must do so using local routing resources which may negatively affect clock performance. Use CLOCK_DEDICATED_ROUTE set to FALSE to indicate this is intended.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Empty tcl collection of nets.
INFO: [Common 17-83] Releasing license: Implementation
5 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully

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Adventurer
Adventurer
1,561 Views
Registered: ‎09-30-2015

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Please correct me if I'm wrong, but I think the issues is the following:

----GTPE2_COMMON_X0Y0.PLL0OUTCLK -> GTPE2_CHANNEL_X0Y3.PLL1CLK

I'm trying to route a signal from the X0Y0 region to a a location in the X0Y3 region.  I'm going to look thru my design to see if I can determine

where the location placements are being made.

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Adventurer
Adventurer
1,541 Views
Registered: ‎09-30-2015

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

It seems like it is trying to route a signal from my PLL in the X0Y0 region over to GTP resources in the X1Y0 region.  While this isn't a problem in the larger p7030, I'm guessing there isn't enough fabric to route this in the 7012.  I would like to try forcing the location of the PLL to the PLLE2_ADV in the X1Y1 region.  If I can get closer to the GTP, I'm hoping it can route the net.  Is there a way to force vivado to use the PLL in the X1Y1 region?x0y0_vs_x1y1_pll.JPG

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Xilinx Employee
Xilinx Employee
1,533 Views
Registered: ‎05-08-2012

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Hi @creedxlnx.

For the original error, I would try lining up the COMMON clock output port number with the CHANNEL input port number. The unroutable connection shows:

-----GTPE2_COMMON_X0Y0.PLL0OUTCLK -> GTPE2_CHANNEL_X0Y3.PLL1CLK

Can you change this to PLL1OUTCLK -> PLL1CLK

By following the Device window connectivity from GTPE2_CHANNEL_X0Y3.PLL1CLK to GTPE2_COMMON_X0Y0.PLL0OUTCLK, I can see that this is a dedicated connection.

You can also constrain these sites to specific locations. For example

set_property LOC GTPE2_CHANNEL_X*Y* [get_cells <cell_name>]


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Adventurer
Adventurer
1,470 Views
Registered: ‎09-30-2015

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

I switched from .PLL0OUT to .PLL1OUT on gtpe2_common, but that somehow cause the unroutable connection to change.

Type 1 : GTPE2_COMMON.PLL1OUTCLK->GTPE2_CHANNEL.PLL0CLK
-----Num Open nets: 1
-----Representative Net: Net[922] ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_i
-----GTPE2_COMMON_X0Y0.PLL1OUTCLK -> GTPE2_CHANNEL_X0Y3.PLL0CLK
-----Driver Term: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_gt_common_i/jesd204_0_common/gtpe2_common_i/PLL1OUTCLK Load Term [5930]: ujesd/ugtx_tx/i_gtx/inst/jesd204_phy_block_i/jesd204_gtx_phy_2_gt/inst/jesd204_gtx_phy_2_gt_i/gt0_jesd204_gtx_phy_2_gt_i/gtpe2_i/PLL0CLK
Ending Interactive Router Task | Checksum: ee8b5d23

I changed the PLL1, but the move to PLL0 on GTPE2_CHANNEL seems to have happened on its own.  I'm double-checking.

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Xilinx Employee
Xilinx Employee
1,439 Views
Registered: ‎05-08-2012

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Hi @creedxlnx.

I would check to see what the connectivity is when opening the earliest build stage (Open Elaborated Design). Is the connectivity correct here? If the connecitivy is being switched during the flow, a DONT_TOUCH constraint could help. If the connectivity does not match at the elaboration stage, the RTL could be checked. 


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Adventurer
Adventurer
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Registered: ‎09-30-2015

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Thanks for the suggesstions. I need to shift over to a different task so I will work on this as time permits. Thanks again.
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Visitor mik3l3_hdl
Visitor
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Registered: ‎08-15-2019

Re: Vivado 2018.2 DRC RTSTAT-2 Partially routed nets

Hi @marcb ,

 

I am implementing a DAC interface to be able to read on the oscilloscope results coming from a Simulation running on Ultrascale vcu118-xcvup9-flga21-2L-e

connected to a TI DAC34H84/SH84.

 

To debug the system Iam running a unit test in which my design is consituted by a top leve design which has only 4 ports which corresponds to :

2 ports of the differential clock fed  in input to the DAC and 2 ports corresponding to the same signal produced in output by the DAC (which in the final design will be used to feed the clock to the FPGA).

I checked my constraint and everything seems fine.  I made sure that all my clocks are latched to Clock Capable pins.  Plust there is the reset port which has been constrained to a LVCMOS18 I/O standard.

This is my constraint file (enclosed between the two #### lines):

#########################################################################################################################################

set_property PACKAGE_PIN AY32 [get_ports dac_clk_to_device_p]
set_property IOSTANDARD LVDS [get_ports dac_clk_to_device_p]
set_property PACKAGE_PIN AY33 [get_ports dac_clk_to_device_n]
set_property IOSTANDARD LVDS [get_ports dac_clk_to_device_n]


set_property PACKAGE_PIN BA16 [get_ports evt]
set_property IOSTANDARD LVCMOS18 [get_ports evt]

 

######################################################################################################################
### GPIO_SW_C IS THE CENTRAL USER PUSHBOTTON (ref. manual ug1224-vcu118-eval-bd.pdf Figure 3-20)
######################################################################################################################
set_property PACKAGE_PIN BD23 [get_ports reset]
set_property IOSTANDARD LVCMOS18 [get_ports reset]
######################################################################################################################


set_property PACKAGE_PIN AJ32 [get_ports data_clk_to_dac_n]
set_property IOSTANDARD LVDS [get_ports data_clk_to_dac_n]
set_property PACKAGE_PIN AK32 [get_ports data_clk_to_dac_p]
set_property IOSTANDARD LVDS [get_ports data_clk_to_dac_p]

#########################################################################################################################################

 

The system is based on a Clock Generator (IP clocking wizard...) and a DDR( Select I/O) . The DDR has only two TX LVDS PINS.

 

The system synthesis and Implementation steps are fine but once i got to the BITSTREAM GENERATION ,  the following error message shows up:

######################################################################################################################################

[DRC RTSTAT-13] Insufficient Routing: A signficant portion of the design is not routed. Routed nets status (RTSTAT-*) DRC checks will not be run. For routing information, run report_route_status. Please run implementation on your design.

In the report shows that 112 nets are failed. 

To get more info i tried to run individually one of those single nets  and finally i ran also the routing status report and i got the following reports

 

route_design -nets [get_nets dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/RX_BIT_CTRL_OUT4[21]]
Command: route_design -nets [get_nets {dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/RX_BIT_CTRL_OUT4[21]}]
Attempting to get a license for feature 'Implementation' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xcvu9p'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Interactive Router Task

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1acb8b45a

Time (s): cpu = 00:02:18 ; elapsed = 00:01:33 . Memory (MB): peak = 5924.594 ; gain = 320.191
INFO: [Route 35-47] Routing for 1 net will be attempted.
Post Restoration Checksum: NetGraph: 318158c2 NumContArr: fa05d5cc Constraints: 0 Timing: 0

Phase 2 Router Initialization
Phase 2 Router Initialization | Checksum: 12b872e8e

Time (s): cpu = 00:02:18 ; elapsed = 00:01:33 . Memory (MB): peak = 5924.594 ; gain = 320.191
Number of Nodes with overlaps = 0
CRITICAL WARNING: [Route 35-276] Interactive router failed to route 1 net.
Resolution: Run report_route_status and review the logfile to identify routing failures.

Unroutable connection Types:
----------------------------
Checking all reachable nodes within 5 hops of driver and load

Unroute Type 1 : Site pin does not reach interconnect fabric

Type 1 BITSLICE_CONTROL.PDQS_OUT4->BITSLICE_RX_TX.RX_CLK_P
-----Num Open nets: 1
-----Representative Net: Net[1] dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/RX_BIT_CTRL_OUT4[21]
-----BITSLICE_CONTROL_X0Y36/PDQS_OUT4 -> BITSLICE_RX_TX_X0Y236/RX_CLK_P
-----Driver Term: dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst/RX_BIT_CTRL_OUT4[21] Load Term [3]: dacInterface/dataClockOut/inst/top_inst/bs_top_inst/u_tx_bs/TX_BS[49].u_tx_bitslice_if_bs/RX_BIT_CTRL_IN[21]
Driver Pin does not reach Interconnect fabric within 5 hops.
Load Pin does not reach Interconnect fabric within 5 hops
Pins Reached within 5 hops from Driver
BITSLICE_RX_TX_X0Y238/RX_CLK_P Net on Pin:
Pins Reached within 5 hops from Load
BITSLICE_CONTROL_X0Y36/PDQS_OUT2 Net on Pin: dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/RX_BIT_CTRL_OUT4[21] Net Driver: BITSLICE_CONTROL_X0Y36/PDQS_OUT4
Ending Interactive Router Task | Checksum: 12b872e8e

Time (s): cpu = 00:02:18 ; elapsed = 00:01:33 . Memory (MB): peak = 5924.594 ; gain = 320.191
INFO: [Common 17-83] Releasing license: Implementation
6 Infos, 0 Warnings, 1 Critical Warnings and 0 Errors encountered.
route_design failed
route_design: Time (s): cpu = 00:02:27 ; elapsed = 00:01:38 . Memory (MB): peak = 5924.594 ; gain = 1237.492
report_route_status
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 615 :
# of nets not needing routing.......... : 364 :
# of internally routed nets........ : 244 :
# of nets with no loads............ : 120 :
# of routable nets..................... : 251 :
# of unrouted nets................. : 112 :
# of fully routed nets............. : 139 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

current_design synth_1
current_design impl_1
current_design synth_1

######################################################################################################################################

 

  

I am completely blocked and i really need your help guys .

 

Thanks a lot

Regards

 

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