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Registered: ‎12-14-2020

Vivado 2018.3 Abnormal program termination (11) during Implementation/opt_design



I am trying to synthesize an opensource  risc-v core on the ZC706 board. The implementation step terminated after "Attempting to get a license for feature 'Implementation' and/or device 'xc7z045'", shown by the log below. I think I have all the licenses installed. If not, Vivado would have complained even before starting the implementation phase.


Finished Parsing XDC File [/mnt/d/ubuntu_workspace/zc706/opentitan/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/src/lowrisc_systems_top_earlgrey_nexysvideo_0.1/data/placement.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 0.000 ; gain = 0.000 ; free physical = 3062 ; free virtual = 26532
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 637 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 39 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 86 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 512 instances

9 Infos, 69 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:34 . Memory (MB): peak = 0.000 ; gain = 0.000 ; free physical = 3062 ; free virtual = 26532
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z045'
Abnormal program termination (11)
Please check '/mnt/d/ubuntu_workspace/zc706/opentitan/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/lowrisc_systems_top_earlgrey_nexysvideo_0.1.runs/impl_1/hs_err_pid27787.log' for details
[Mon Dec 14 19:55:42 2020] impl_1 finished
wait_on_run: Time (s): cpu = 00:09:32 ; elapsed = 00:11:32 . Memory (MB): peak = 0.000 ; gain = 0.000 ; free physical = 4401 ; free virtual = 27870
Bitstream generation completed
ERROR: Implementation and bitstream generation step failed.
INFO: [Common 17-206] Exiting Vivado at Mon Dec 14 19:55:42 2020...
make: *** [Makefile:14: lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit] Error 1



The original project which compiled successfully was using the Nexys Video board. I am porting it to the ZC706 board. I modified the top level module and the constraint file accordingly. My changes are mainly disabling the unavailable peripherals and using the differential clock on the board. 

The "hs_err_pid27787.log" log is attached. I cannot understand anything from this file. Therefore, any help is greatly appreciated!


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2 Replies
Registered: ‎12-14-2020

The changed RTL and constraint files are attached here.

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Xilinx Employee
Xilinx Employee
Registered: ‎01-30-2019

Hi @jakeke 

Is it possible for you to share the design with me?  I would like to reproduce the issue at my end and debug further.
Please share your email ID so that I can send an ezmove package for secure transfer of the design.

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