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Explorer
Explorer
538 Views
Registered: ‎09-14-2018

Vivado 2018.3 false camplaint on IO standard

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Hello,

I have KCU105 Ultrascale evaluation board and use Vivado 2018.3.

Implementation of my design failed due to two lines in the constraint file:  

set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TP[*]}]

get_property IOSTANDARD LVCMOS12 [get_ports {FPGA_DIPSW[*]}]

Here is the message:

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 45. For example, the following two ports in this bank have conflicting VCCOs: FPGA_TP[0] (LVCMOS12, requiring VCCO=1.200) and FPGA_DIPSW[0] (LVCMOS18, requiring VCCO=1.800)

 

FPGA_TP[*] are PMOD0/1* nets on KCU105 board.

FPGA_DIPSW[*] are GPIO_DIP_SW* nets.

All of them are hooked up to the bank 45, used for DDR4 and powered by 1.2V. The error messages do not make sense. Any idea why?  

Thank you.

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Xilinx Employee
Xilinx Employee
412 Views
Registered: ‎11-30-2007

Vivado assumes any single-ended IO not defined with an IOSTANDARD constraint is LVCMOS18 and any differential IO not defined with an IOSTANDARD is LVDS.  My guess is that your constraints are not correct and IOs are defaulting to LVCMOS18... or there are a couple IOs that were placed in the IO Bank that did not have an IOSTANDARD assigned which is causing an IO Banking incompatibility.  You will want to reference the Rules for Combining I/O Standards in the Same Bank section of UG571.

You referenced the following from your constraints file:

set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TP[*]}]
get_property IOSTANDARD LVCMOS12 [get_ports {FPGA_DIPSW[*]}]

I think the first line should be as follows.  Remove the '{' and '}' brackets.

set_property IOSTANDARD LVCMOS12 [get_ports FPGA_TP[*]]

The second line should be set_property and not get_property.  I would suggest the second line be as follows.  Change get_property to set_property and remove the '{' and '}' brackets.

set_property IOSTANDARD LVCMOS12 [get_ports FPGA_DIPSW[*]]

You can also open up your implemented design and view the "I/O Ports" tab to see if each IO pin is marked as "fixed" indicating a PACKAGE_PIN constraint was properly found... and look for the I/O Standard Column to NOT have an asterisk (*) which would indicate a default I/O Standard versus an IOSTANDARD constraint was properly found.

forums_io_ports_1.png

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Xilinx Employee
Xilinx Employee
460 Views
Registered: ‎01-30-2019

Hi @arotenst 

please have a look at this and let us know if it helps? https://www.xilinx.com/support/answers/64450.html

 

 

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Explorer
Explorer
429 Views
Registered: ‎09-14-2018

Hello,

That did not help. I changed LVCMOS12 to LVCMOS18 (with the actual voltage VCC0 1.2V), and that helped.

Vivado does not know that the bank is powered by 1.2V. It assumes 1.8V. Secondly, the message it generates is wrong and confusing.

How to let Vivado know about the true bank IO voltage?

Thank you.

 

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Xilinx Employee
Xilinx Employee
413 Views
Registered: ‎11-30-2007

Vivado assumes any single-ended IO not defined with an IOSTANDARD constraint is LVCMOS18 and any differential IO not defined with an IOSTANDARD is LVDS.  My guess is that your constraints are not correct and IOs are defaulting to LVCMOS18... or there are a couple IOs that were placed in the IO Bank that did not have an IOSTANDARD assigned which is causing an IO Banking incompatibility.  You will want to reference the Rules for Combining I/O Standards in the Same Bank section of UG571.

You referenced the following from your constraints file:

set_property IOSTANDARD LVCMOS12 [get_ports {FPGA_TP[*]}]
get_property IOSTANDARD LVCMOS12 [get_ports {FPGA_DIPSW[*]}]

I think the first line should be as follows.  Remove the '{' and '}' brackets.

set_property IOSTANDARD LVCMOS12 [get_ports FPGA_TP[*]]

The second line should be set_property and not get_property.  I would suggest the second line be as follows.  Change get_property to set_property and remove the '{' and '}' brackets.

set_property IOSTANDARD LVCMOS12 [get_ports FPGA_DIPSW[*]]

You can also open up your implemented design and view the "I/O Ports" tab to see if each IO pin is marked as "fixed" indicating a PACKAGE_PIN constraint was properly found... and look for the I/O Standard Column to NOT have an asterisk (*) which would indicate a default I/O Standard versus an IOSTANDARD constraint was properly found.

forums_io_ports_1.png

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Explorer
Explorer
347 Views
Registered: ‎09-14-2018

Thank you, Mike.

get_property was a typo I missed. No complains on IOSTANDARD now.

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Observer
Observer
183 Views
Registered: ‎03-21-2011

the fact that "get_property" here doesn't pop a huge red error or critical warning. It's so nonsensical to the compiler that it should just halt.  You're saying it skips over it and just keeps chugging along?  "I don't understand what the user tried to tell me here, so I'll just silently ignore it"?  No wonder people pull their hair out over constraints.

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Explorer
Explorer
166 Views
Registered: ‎09-14-2018

Both FPGA_TP and FPGA_DIPSW arrays were assigned to the same 1.2 V bank. You can make an experiment. If you have a project with two signals assigned to 1.2V bank and do not set_property for one of them. See what you'll get. The results might be different for different Vivado versions. My guess.  

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