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Observer jays_xil
Observer
606 Views
Registered: ‎01-09-2013

Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

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Hi all, 

For Vivado 2018.3 in Windows 10  I am getting C2M TX pin placement issues and bitstream DRC error for a design using zcu106 dev board..In Vivado 2018.2.1 this design works and properly places C2M TX data ports per constrains xdc file with no errors.

In Vivado 2018.3 the last four of the eight C2M TX diff data ports appear not to have package pin Fixed checked in Implemented Device view and two of these diff pairs have their pin locations swapped. The bitstream DRC check also generates errors saying these last four C2M TX data ports do not have physical locations assigned to them, but they are in my constrains xdc file just like the first four. This is the same xdc file that works in 2018.2.1.

Design is using zynq ultrascale+ zcu106 dev board, these are the C2M ports to HPC FMC card.    

This is the section of my constrains xdc file. 

#setup TX pins to match DAC 0 to 7 C2M ports

set_property -dict {PACKAGE_PIN L6} [get_ports {tx_data_p[0]}]

set_property -dict {PACKAGE_PIN L5} [get_ports {tx_data_n[0]}]

set_property -dict {PACKAGE_PIN M4} [get_ports {tx_data_p[1]}]

set_property -dict {PACKAGE_PIN M3} [get_ports {tx_data_n[1]}]

set_property -dict {PACKAGE_PIN H4} [get_ports {tx_data_p[2]}]

set_property -dict {PACKAGE_PIN H3} [get_ports {tx_data_n[2]}]

set_property -dict {PACKAGE_PIN K4} [get_ports {tx_data_p[3]}]

set_property -dict {PACKAGE_PIN K3} [get_ports {tx_data_n[3]}] 

set_property -dict {PACKAGE_PIN U6} [get_ports {tx_data_p[4]}]

set_property -dict {PACKAGE_PIN U5} [get_ports {tx_data_n[4]}]

set_property -dict {PACKAGE_PIN N6} [get_ports {tx_data_p[5]}]

set_property -dict {PACKAGE_PIN N5} [get_ports {tx_data_n[5]}]

set_property -dict {PACKAGE_PIN T4} [get_ports {tx_data_p[6]}]

set_property -dict {PACKAGE_PIN T3} [get_ports {tx_data_n[6]}]

set_property -dict {PACKAGE_PIN R6} [get_ports {tx_data_p[7]}]

set_property -dict {PACKAGE_PIN R5} [get_ports {tx_data_n[7]}]

 

2018.3 Bitstream DRC error

UCIO #1 Critical Warning 8 out of 198 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: tx_data_n[7], tx_data_n[6], tx_data_n[5], tx_data_n[4], tx_data_p[7], tx_data_p[6], tx_data_p[5], tx_data_p[4].

 SInce Vivado 2018.3 does not seem to work correctly with my constrains xdc file but did work correctly in 2018.2.1 I assume someone at Xilinx made some change that broke the tool. 

 This a very large design that drives a AD9136 JESD204B DAC FMC card.

 Is there a different way to set the C2M TX pin outs in my constrains xdc file that might work? 

Thanks,

James 

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Observer jays_xil
Observer
497 Views
Registered: ‎01-09-2013

Re: Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

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Hi MarcB,

   In the Synthesized design I get a warning message, I had not noticed it before, that the external PCIe interface, XDMA IP, I also have thinks it is using the given GTH bank for the upper 4 JESD204B port pins.

 This is somewhat odd since the Synthesized design Device View and I/O ports shows the PCIe pin being properly placed at their assigned fixed location in the GTH Quad Common bank X0Y1 and the upper 4 JESD204B port pins placed in GTH Quad Common bank X0Y3 where they should be but with unfixed pin locations.

 I am setting the XDMA 4.1 IP for PCIe up in my TCL build file to use config.pcie_blk_locn  {X0Y1}, I can see this is being set in Block Design on the Basic tab selection for PCIe, XDMA:4.1 IP.  GTH common bank X0Y1 being the correct GTH bank to locate the PCIe in for the zcu016 board. Note this is also the default location the XDMA IP sets for the zcu106 board.  

  Whereas the GTH common block X0Y3 is for the FMC connector I have the upper 4 JESD204B port pins in question on. That is 2018.3 Vivado synthesis for some reason is not seeing that the XDMA PCIe IP 4.1 is setup to use the GTH common block X0Y1 in the first place whereas Vivado 2018.2.1 does.

  In my pinout XDC file I had fixed locations for the JESD204B port pins setup before I setup fix the pin locations for the external PCIe interface.  I am now running an XDC file with PCIe fixed pin locations first in it.

  Declaring the PCIe interface pinout first before the JESD204B pinout in XDC, fixes the problem I now see all of my GTH TX ports in an 8 port JESD204B design at their proper fix pin locations.

  It appears to be a XDMA 4.1 IP issue for the zcu106 dev board, zcu7ev-ffvc1156-2-e device in 2018.3 that was not present in 20182.1. That is 2018.3 Vivado Is trying to place the Xilinx XDMA PCIe into GTH common bank X0Y3 and not the X0Y1 bank it has been told to place in.   

 I am just glad the moving the PCIe fixed pin placement in the XDC file to be before the 8 port JESD204B fixed pin placement seems to fix the issue.

Thanks,

James

 

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Xilinx Employee
Xilinx Employee
540 Views
Registered: ‎05-08-2012

Re: Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

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Hi @jays_xil

The LOC constraint is an alternative to the PACKAGE_PIN constraint, and could be used instead. I would check the synthesis and implementation log to see if there are any clues as to why the constraints were not applied.


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Observer jays_xil
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Registered: ‎01-09-2013

Re: Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

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Hi marcb,

 Well I tried to see using LOC worked but it does the same thing; the first four of the GTH pins get placed in the first quad but the last four GTH in the second quad do not show as being placed in the synthesized device IO Ports tab. If I manual place the last four in I/O ports it generates a XDC file which uses set_property PACKAGE_PIN N6 [get_ports {tx_data_p[5]}]... just like I had before. 

 Again this all worked correctly in 2018.2.1 Vivado with no issues. 

Something in 2018.3 does not seem to allow placement in the second GTH quad bank for the zynq ultrascale+ zcu7ev type device. 

GTH quad that works is I/O Bank 227

GTH quad that does not allow pin placement is I/O Bank  226

Is there a way to report this issue in 2018.3 to the Xilinx design team ?

Thanks,

James  

set_property LOC L6 [get_ports {tx_data_p[0]}]
set_property LOC M4 [get_ports {tx_data_p[1]}]
set_property LOC H4 [get_ports {tx_data_p[2]}]
set_property LOC K4 [get_ports {tx_data_p[3]}]

set_property LOC U6 [get_ports {tx_data_p[4]}]
set_property LOC N6 [get_ports {tx_data_p[5]}]
set_property LOC T4 [get_ports {tx_data_p[6]}]
set_property LOC R6 [get_ports {tx_data_p[7]}]
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Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎05-08-2012

Re: Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

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Hi @jays_xil

I have just sent a private message so that the design can be transferred, and reviewed. I can review the Vivado behavior.

Marc

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Observer jays_xil
Observer
498 Views
Registered: ‎01-09-2013

Re: Vivado 2018.3 in Windows 10 C2M TX pin placement issues and bitstream DRC error

Jump to solution

Hi MarcB,

   In the Synthesized design I get a warning message, I had not noticed it before, that the external PCIe interface, XDMA IP, I also have thinks it is using the given GTH bank for the upper 4 JESD204B port pins.

 This is somewhat odd since the Synthesized design Device View and I/O ports shows the PCIe pin being properly placed at their assigned fixed location in the GTH Quad Common bank X0Y1 and the upper 4 JESD204B port pins placed in GTH Quad Common bank X0Y3 where they should be but with unfixed pin locations.

 I am setting the XDMA 4.1 IP for PCIe up in my TCL build file to use config.pcie_blk_locn  {X0Y1}, I can see this is being set in Block Design on the Basic tab selection for PCIe, XDMA:4.1 IP.  GTH common bank X0Y1 being the correct GTH bank to locate the PCIe in for the zcu016 board. Note this is also the default location the XDMA IP sets for the zcu106 board.  

  Whereas the GTH common block X0Y3 is for the FMC connector I have the upper 4 JESD204B port pins in question on. That is 2018.3 Vivado synthesis for some reason is not seeing that the XDMA PCIe IP 4.1 is setup to use the GTH common block X0Y1 in the first place whereas Vivado 2018.2.1 does.

  In my pinout XDC file I had fixed locations for the JESD204B port pins setup before I setup fix the pin locations for the external PCIe interface.  I am now running an XDC file with PCIe fixed pin locations first in it.

  Declaring the PCIe interface pinout first before the JESD204B pinout in XDC, fixes the problem I now see all of my GTH TX ports in an 8 port JESD204B design at their proper fix pin locations.

  It appears to be a XDMA 4.1 IP issue for the zcu106 dev board, zcu7ev-ffvc1156-2-e device in 2018.3 that was not present in 20182.1. That is 2018.3 Vivado Is trying to place the Xilinx XDMA PCIe into GTH common bank X0Y3 and not the X0Y1 bank it has been told to place in.   

 I am just glad the moving the PCIe fixed pin placement in the XDC file to be before the 8 port JESD204B fixed pin placement seems to fix the issue.

Thanks,

James

 

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