Block diagram attached, this project works under 2016.3 (i.e. runs on hardware). The issue is (nominally) with Vivado 2020.1.
[Place 30-58] is reported "IO placement is infeasible" with all the I2sBram Block Pins and some S_AXI pins cited as violators.
My take is that Vivado wants to attach these pins to IO pads, but has run out of victims, only 110 of 120 sites required available ...
There is of course no design requirement to take these signals to IO, if there was there would be corresponding External Ports.
0) This looks like a prima facie bug in Vivado 2020.1
1) Is there a workaround or best / necessary practice which should be followed
2) What version of Vivado do I have to regress to to dodge this "feature"
The project archive could be provided in confidence, but not on this forum
My error ...
That old favorite - the bd wrapper was not at the top of the heirarchy.
Indeed, it had not been generated.
Generate the wrapper and ensure its at the top of the pile : seems fine
0) walking away from problems (helps to) solve them
1) it would be nice if Vivado
a) prompted wrapper generation - when it obviously "needs" to be done
b) commented on the abscence of a wrapper when its probably omitted