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Observer
Observer
739 Views
Registered: ‎11-13-2017

Vivado : Bus signals were split up into single signal in the .LTX file

Nowdays, I am debugging the my design with vivado ILA.

I don't want to use the vivao project mode, and I don't want to change my verilog source code for debugging. 

So I only used the TCL script to insert ILA.

everything is okay. But I have a one problem. 

When I open waveform with .ltx on the vivado, All bus signals were split up into single signals.

* This is small part of my .xdc. *

-----------------------------------------------------------------------------------------------------------------------

#create the debug core
create_debug_core instruction_memory_debug ila

#set debug core property
set_property C_DATA_DEPTH 1024 [get_debug_cores instruction_memory_debug]
set_property C_TRIGIN_EN false [get_debug_cores instruction_memory_debug]
set_property C_TRIGOUT_EN false [get_debug_cores instruction_memory_debug]
set_property C_ADV_TRIGGER false [get_debug_cores instruction_memory_debug]
set_property C_INPUT_PIPE_STAGES 3 [get_debug_cores instruction_memory_debug]
set_property C_EN_STRG_QUAL false [get_debug_cores instruction_memory_debug]
set_property ALL_PROBE_SAME_MU true [get_debug_cores instruction_memory_debug]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores instruction_memory_debug]

set_property port_width 1 [get_debug_ports instruction_memory_debug/clk]
connect_debug_port instruction_memory_debug/clk [get_pins [list topDesign/topMod/clock]]

set_property mark_debug true [get_nets [list {topDesign/topMod/io_channel_out_flit_bits_virtual_channel_id_bits[0]} {topDesign/topMod/o_channel_out_flit_bits_virtual_channel_id_bits[1]}]]

create_debug_port instruction_memory_debug probe
set_property port_width 2 [get_debug_ports instruction_memory_debug/probe4]
set_property PROBE_TYPE DATA [get_debug_ports instruction_memory_debug/probe4]
connect_debug_port instruction_memory_debug/probe4 [get_pins [list {topDesign/topMod/io_channel_out_flit_bits_virtual_channel_id_bits[0]} {topDesign/topMod/io_channel_out_flit_bits_virtual_channel_id_bits[1]}]]

-----------------------------------------------------------------------------------------------------------------------

As you can see, I assign "mark_debug" to preserve signals that I want to debug and port_width is 2.

* this is small part of .ltx *

-----------------------------------------------------------------------------------------------------------------------

<probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_DATA_V2_RT">
  <probeOptions Id="DebugProbeParams">
    <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
   <Option Id="CORE_LOCATION" value="1:1"/>
   <Option Id="CORE_UUID" value="00000000000000000000000000000000"/>
   <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="75007508"/>
   <Option Id="HW_ILA" value="instruction_memory_debug"/>
   <Option Id="PROBE_PORT" value="4"/>
   <Option Id="PROBE_PORT_BITS" value="0"/>
   <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
<probeOptions>
<nets>
    <net name="io_channel_out_flit_bits_virtual_channel_id_bits[0]_instruction_memory_debug"/>
<nets>
<probe>
<probe type="ila" busType="net" source="netlist" spec="ILA_DATA_V2_RT">
  <probeOptions Id="DebugProbeParams">
    <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
    <Option Id="CORE_LOCATION" value="1:1"/>
    <Option Id="CORE_UUID" value="00000000000000000000000000000000"/>
    <Option Id="HUB_CLK_INPUT_FREQ_HZ" value="75007508"/>
    <Option Id="HW_ILA" value="instruction_memory_debug"/>
    <Option Id="PROBE_PORT" value="4"/>
    <Option Id="PROBE_PORT_BITS" value="1"/>
    <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
<probeOptions>
<nets>
    <net name="io_channel_out_flit_bits_virtual_channel_id_bits[1]_instruction_memory_debug"/>
<nets>
<probe>

-----------------------------------------------------------------------------------------------------------------------

As you can see, The PROBE_PORT_BIT_COUNT is always "1". 

I think All bus signals were split up into single signals on the waveform Because of this option.

I make the .ltx file after "opt_design" command.

please let me know to fix this problem.

thanks.

 

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3 Replies
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Xilinx Employee
Xilinx Employee
725 Views
Registered: ‎05-22-2018

Hi @uramashi2 ,

Try with using dictionary sort on the nets.

connect_debug_port ila1/probe0 [lsort -dictionary [get_nets [list $ila_nets ]]]

This should help in correctly grouping the signals.

Thanks,

Raj

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Observer
Observer
713 Views
Registered: ‎11-13-2017

Thank for reply.

But I got this error message when I applied the command that you mentioned.

------------------------------------------------------------------------------------------

"Command 'lsort' is not supported in the xdc constraint file."

------------------------------------------------------------------------------------------

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Xilinx Employee
Xilinx Employee
706 Views
Registered: ‎05-22-2018

Hi @uramashi2 ,

Try to apply through tcl console, please check the AR# link:

https://www.xilinx.com/support/answers/54842.html

Thanks,

Raj

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