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Registered: ‎04-09-2008

Vivado Constraints and Logic Optimization

ug904 page 51 says:

"... Logic optimization also skips optimization of design objects that have directly applied timing constraints and exceptions. This prevents constraints from being lost when their target objects are optimized away from the design..."

Sometimes I find writing RTL with fixed sized ranges more easily understood and flexible versus using generics or unconstrained vectors. Most of the time I can rely on synthesis and optimization to propagate constants and sweep the unused logic away. In a few specific instances I've applied set_multicycle_path constraints to or from a 64 bit wide signal bus where only sparse mapping of those registers are not constant zero. I was surprised to find all bits of that large signal bus in my implementation design checkpoints. Looking at the schematic in the design checkpoint, I can trace that signal back multiple levels of registers, back to a flip-flop that is initialized to 1b0 and whose inputs can only ever set the state to 1b0.

What is the purpose of preventing logic optimization on signals with timing exceptions directly applied? Is there some way to instruct opt_design to NOT do that, and optimize them anyway? Has anyone else run into a similar situation and have advice how to work-around it?


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Registered: ‎11-04-2010

The constraints is to set the requirement for the design and tool should honor these requirement all the time.

The object which is referred by a constraint will be reserved and the purpose of the behavior is to reserve the user constraints. If the referred objects is removed, the related constraints will be invalid. Changing the user's constraints is not allowed.

The user cannot  instruct opt_design NOT to sweep the referred object. Please avoid referring to the objects which has risky to be optimized away in your constraints.

Don't forget to reply, kudo, and accept as solution.