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Visitor joelee888
Visitor
202 Views
Registered: ‎05-25-2018

Vivado GUI doesn't show connectivity of routed pins

After I finished PnR using Vivado v2018.2 targeting to FPGA XC7VX690TFFG1761-3, I tried to show connectivity of a flop output pin in GUI, but nothing was showed. Cell Pin Properties window indicated the pin was routed. Is it a tool limitation that not all connectivity can be showed? Is the pin physically routed actually?

Thanks,

Joe Lee

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5 Replies
Moderator
Moderator
196 Views
Registered: ‎01-16-2013

Re: Vivado GUI doesn't show connectivity of routed pins

@joelee888

 

You need to Open the implemented design and not synthesized design to see the routed nets connectivity.

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor joelee888
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177 Views
Registered: ‎05-25-2018

Re: Vivado GUI doesn't show connectivity of routed pins

Actually, I opened the checkpoint which was generated after "eval route_design" was done (synthesis, place and routing were all done by batch mode scripts on Linux). So I think I am reading an implemented design, am I not?

Thanks,

Joe Lee

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Historian
Historian
167 Views
Registered: ‎01-23-2009

Re: Vivado GUI doesn't show connectivity of routed pins

When you say "the checkpoint which was generated after 'eval route_design'" do you mean that the script did

eval route_design
write_checkpoint <name_of_dcp_file>

When running in non-project mode, everything is done "in memory", so you will not get a routed .dcp file unless you do a write_dcp after the route_design command is complete.

But back to your question - the GUI definitely can (and does) show the route connectivity in a routed design. There are actually two modes - one where the route is shown as pure connectivity (a straight line showing the connection from the driver to the receiver) and another showing the detailed routing resources. They are toggled by a push button on the toolbar:

RoutingResources.jpg

Avrum

Moderator
Moderator
159 Views
Registered: ‎01-16-2013

Re: Vivado GUI doesn't show connectivity of routed pins

@joelee888

 

Please see above post from avrum. You can run report_route_status command in Vivado TCL console to know if the design has successfully routed all the nets. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug835-vivado-tcl-commands.pdf#page=1376

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Visitor joelee888
Visitor
96 Views
Registered: ‎05-25-2018

Re: Vivado GUI doesn't show connectivity of routed pins

Avrum,

1. Yes, we did 'eval route_design' followed by 'write_checkpoint'. I can't find 'write_dcp' in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug835-vivado-tcl-commands.pdf, and I'm using Vivado 2018.2.

2. I am able to see the routing connection of the flop output that I am interested in 'detail routing resources' mode. However, I don't see the connectivity line in 'connectivity' mode. Do you know why?

Syed,

Thanks for the link.

 

Thanks,

Joe

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