01-07-2019 06:55 AM
After I finished PnR using Vivado v2018.2 targeting to FPGA XC7VX690TFFG1761-3, I tried to show connectivity of a flop output pin in GUI, but nothing was showed. Cell Pin Properties window indicated the pin was routed. Is it a tool limitation that not all connectivity can be showed? Is the pin physically routed actually?
01-07-2019 06:59 AM
You need to Open the implemented design and not synthesized design to see the routed nets connectivity.
01-07-2019 07:44 AM
Actually, I opened the checkpoint which was generated after "eval route_design" was done (synthesis, place and routing were all done by batch mode scripts on Linux). So I think I am reading an implemented design, am I not?
01-07-2019 08:05 AM
When you say "the checkpoint which was generated after 'eval route_design'" do you mean that the script did
When running in non-project mode, everything is done "in memory", so you will not get a routed .dcp file unless you do a write_dcp after the route_design command is complete.
But back to your question - the GUI definitely can (and does) show the route connectivity in a routed design. There are actually two modes - one where the route is shown as pure connectivity (a straight line showing the connection from the driver to the receiver) and another showing the detailed routing resources. They are toggled by a push button on the toolbar:
01-07-2019 08:21 AM
Please see above post from avrum. You can run report_route_status command in Vivado TCL console to know if the design has successfully routed all the nets.
01-09-2019 06:09 AM
1. Yes, we did 'eval route_design' followed by 'write_checkpoint'. I can't find 'write_dcp' in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug835-vivado-tcl-commands.pdf, and I'm using Vivado 2018.2.
2. I am able to see the routing connection of the flop output that I am interested in 'detail routing resources' mode. However, I don't see the connectivity line in 'connectivity' mode. Do you know why?
Thanks for the link.