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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Vivado: IBUFDS_GTE2 driven by IBUF?

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Hi folks,

 

  While building an OOC module in Vivado using the HD flow, I'm getting this DRC violation and can't find any information about it.

 

ERROR: [Drc 23-20] Rule violation (REQP-1619) IBUFDS_GTE2_driven_by_IBUF - IBUFDS_GTE2 refclk_ibuf pins I and IB should be driven by IBUFs.

 

  Looking at the netlist, the IBUFDS_GTE2 instance is connected to input pads, ie. no IBUF. And according to the transceivers user guide, there should be no IBUF there, just top level ports.  Perhaps this assumes that the top level synthesis will infer two IBUFs automatically there? In this case, the OOC module should instantiate IBUFs. Is this assumption correct?

 

Thanks in advance,

-Pat

 

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vemulad
Xilinx Employee
Xilinx Employee
19,155 Views
Registered: ‎09-20-2012
Hi Pat,

As the error comes up when you run implementation on ooc module, you need to instantiate buffers inside the ooc module.

The top level synthesis will typically infer IO buffers on all top level ports. However, if IO buffers are specifically instantiated in an OOC module, you must turn off IO buffer insertion in the top-level synthesis on a port-by-port basis.

For Vivado synthesis, the attribute to do this is BUFFER_TYPE. For more information on BUFFER_TYPE qplease refer to the Vivado Design Suite User Guide: Synthesis (UG901).

Thanks,
Deepika.
Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
13,351 Views
Registered: ‎09-20-2012

Hi Pat,

 

The primitive IBUFDS_GTE2 primitive needs IBUF inserted on the I and IB pins for it to be properly placed. 

 

In your case as you have set the module as OOC the synthesis will not insert IBUF on the module ports and hence the error.

 

You need to instantiate IBUF in th HDL so that it looks like below.

 

Capture.JPG

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
vemulad
Xilinx Employee
Xilinx Employee
19,156 Views
Registered: ‎09-20-2012
Hi Pat,

As the error comes up when you run implementation on ooc module, you need to instantiate buffers inside the ooc module.

The top level synthesis will typically infer IO buffers on all top level ports. However, if IO buffers are specifically instantiated in an OOC module, you must turn off IO buffer insertion in the top-level synthesis on a port-by-port basis.

For Vivado synthesis, the attribute to do this is BUFFER_TYPE. For more information on BUFFER_TYPE qplease refer to the Vivado Design Suite User Guide: Synthesis (UG901).

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

arcw4650
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Registered: ‎11-23-2019

think for your answer!!it's useful

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