Vivado Implementation (2018.3 and later): Applying IOB TRUE property on registers results in input register failing to place

[opal-rt_fpga_grp]

Vivado Implementation (2018.3 and +): Applying IOB TRUE property on registers results in input register failing to place

In my design, the property IOB=TRUE is applied to the registers connected to I and O pins of a OBUFT as shown in the attachment. During place_design, the following error occurs and the register cannot be placed properly.

ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed
ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder/register6/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed
ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder/register7/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed
ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder1/register5/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed
ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder1/register6/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed
ERROR: [Place 30-68] Instance te0741_3/fpga_model_cw_i0/fpga_model_cw_struct/op5369_1b/encoder_input_subsection/quad_decoder1/register7/synth_reg_inst/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp (FDRE) is not placed

How can I resolve this issue?

Note: don't have this issue when using Vivado 2018.2. Error occurs only for Vivado 2018.3 and later.

[miker]

@opal-rt_fpga_grp If possible, sending the Vivado Project Archive (File > Project > Archive...) would help quickly identify the issue. 

[opal-rt_fpga_grp]

Sorry at this point we are worry about confidentiality. We cannot put a complete design on a public domain. We will try to come up with a trivial case. If this cannot be done, is it possible to go through a private support channel?

[hongh]

Please confirm all these registers which are intended to be placed in the same IOB have the exactly same control signals. 

[opal-rt_fpga_grp]

If you are referring to control signals driving the T input of the IOBUF, then Control signals are all different.

As stated earlier, the design compiled successfully with 2018.2, but not with 2018.3 and later.

[opal-rt_fpga_grp]

Here is a simple trivial test case. Miker and hongh can you take a look.

1- Unzip the archive

2- open Vivado 2018.3

3- Inside vivado (tcl console), cd to folder where you unzip the archive.

4- open_checkpoint test_io_packing_synth.dcp

5- source test_io_packing_constraint.tcl

6- opt_design

7- place_design

You will get this error:

ERROR: [Place 30-68] Instance sv_din_reg[0] (FDRE) is not placed
ERROR: [Place 30-68] Instance sv_din_reg[1] (FDRE) is not placed
ERROR: [Place 30-68] Instance sv_din_reg[2] (FDRE) is not placed
ERROR: [Place 30-68] Instance sv_din_reg[3] (FDRE) is not placed
ERROR: [Place 30-68] Instance sv_din_reg[4] (FDRE) is not placed
ERROR: [Place 30-68] Instance sv_din_reg[5] (FDRE) is not placed

[miker · Accepted solution]

@opal-rt_fpga_grp 

Your tcl hook script generated the following constraints which defined each input FF and each output FF.  In general, this should work.

set_property IOB TRUE [get_cells {sv_count_1d_reg[0]}]
set_property IOB TRUE [get_cells {sv_din_reg[0]}]
set_property IOB TRUE [get_cells {sv_count_1d_reg[1]}]
set_property IOB TRUE [get_cells {sv_din_reg[1]}]
set_property IOB TRUE [get_cells {sv_count_1d_reg[2]}]
set_property IOB TRUE [get_cells {sv_din_reg[2]}]
set_property IOB TRUE [get_cells {sv_count_1d_reg[3]}]
set_property IOB TRUE [get_cells {sv_din_reg[3]}]
set_property IOB TRUE [get_cells {sv_count_1d_reg[4]}]
set_property IOB TRUE [get_cells {sv_din_reg[4]}]
set_property IOB TRUE [get_cells {sv_count_1d_reg[5]}]
set_property IOB TRUE [get_cells {sv_din_reg[5]}]

I typically use get_ports rather than define each of the individual FFs with get_cells so it grabs all the registers possible rather than having to define each one.  Can you please try the following as an alternative?

set_property IOB TRUE [get_ports iov_data[0]]
set_property IOB TRUE [get_ports iov_data[1]]
set_property IOB TRUE [get_ports iov_data[2]]
set_property IOB TRUE [get_ports iov_data[3]]
set_property IOB TRUE [get_ports iov_data[4]]
set_property IOB TRUE [get_ports iov_data[5]]