UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
1,678 Views
Registered: ‎03-31-2016

Vivado [Place 30-675] issue

Jump to solution

Hello

 

Running vivado to P&R will report error message:

 

But my constraint configure GCIO, why vivado report this error message?

 

How to resolve this issue?

 

Vivado: 2017.2

 FPGA device: VU440FLGA2892-1-c

Constraint:

set_property PACKAGE_PIN AF49 [get_ports {XSYS_CLK_0}]
set_property PACKAGE_PIN AF48 [get_ports {XSYS_CLK}]

Vivado Log:

INFO: [Timing 38-35] Done setting XDC timing constraints.
ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
        < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets SYS_CLK_ibufgds/O] >

        SYS_CLK_ibufgds/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y281 (in SLR 1)
        The loads are distributed to 1 user pblock constraints. In addition, there are 20 loads not in user pblock constraints.

        Displaying only the first 20 or fewer instances under each constraint as list of loads is too long

 Displaying first 20 loads not in user pblock constraint: 
../u_global/u_gating/u_clock_gate_global_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y116 (in SLR 0)
../u_global/u_gating/u_clock_gate_global/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y117 (in SLR 0)
../stack0.u_sc_stack_0/tile0.u_sc_tile0/u_shader_tile_gating/u_clock_gate_sc/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y118 (in SLR 0)
../cg.u_cg_async/u_core_group/u_gating/stack0.u_clock_gate_stack0_stack/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y138 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_mmu/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y140 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_tiler_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y119 (in SLR 0)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_tiler/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y143 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_pmb_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y142 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_pmb/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y141 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[11].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y122 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[4].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y130 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[12].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y123 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[1].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y128 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[8].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y134 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[7].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y133 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[13].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y124 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[6].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y132 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[0].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y120 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[9].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y135 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[15].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y126 (in SLR 1)

Displaying the first 8 loads for pblock constraint 1
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[10].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y121 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[14].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y125 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[3].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y129 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[16].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y127 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.gen_l20_ram[5].cond_ram.u_clock_gate_l2_0_ram/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y131 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.u_clock_gate_l2_0_ramif/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y137 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/clock_gate_l20.u_clock_gate_l2_0/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y136 (in SLR 1)
../cg.u_cg_async/u_core_group/u_gating/u_clock_gate_cg/U_CLKGATE (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y139 (in SLR 1)

schematic.JPG

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
2,018 Views
Registered: ‎03-31-2016

Re: Vivado [Place 30-675] issue

Jump to solution

Hello @syedz @marcb

 

This issue is my design used 171 BUFG, so vivado can't placement complete and report this error message.

 

Reduce design BUFG can resolve this issue.

0 Kudos
8 Replies
Moderator
Moderator
1,629 Views
Registered: ‎01-16-2013

Re: Vivado [Place 30-675] issue

Jump to solution

@quincyq2003,

 

Can you share the location of IO and BUFG? Please see the following answer record: 

https://www.xilinx.com/support/answers/66659.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
1,620 Views
Registered: ‎03-31-2016

Re: Vivado [Place 30-675] issue

Jump to solution

Hello @syedz

IO location is IOB_X0Y281

BUFG is BUFGCE_X0Y124

schematic_2.JPG

0 Kudos
Moderator
Moderator
1,609 Views
Registered: ‎01-16-2013

Re: Vivado [Place 30-675] issue

Jump to solution

@quincyq2003,

 

The IO is clock capable (GCIO) and also the BUFG is in same clock region (X0Y5). 

Capture.JPG

 

Can you share the post opt dcp file to debug the issue? 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
1,594 Views
Registered: ‎03-31-2016

Re: Vivado [Place 30-675] issue

Jump to solution

Hello @syedz

 

I can't share the dcp for you.

 

Could you provide resolve method, may be i can resolve this issue.

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
1,571 Views
Registered: ‎05-08-2012

Re: Vivado [Place 30-675] issue

Jump to solution

Hi @quincyq2003. Is the full log file as well as the physical constraints related to the clock path and pblocks available? A simple test using the same primitives, connectivity, and placement did not reproduce.

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

0 Kudos
Explorer
Explorer
1,531 Views
Registered: ‎03-31-2016

Re: Vivado [Place 30-675] issue

Jump to solution

Hello @marcb@syedz

 

This issue is resolve.

 

Thanks for your help!!

 

 

 

0 Kudos
Moderator
Moderator
1,501 Views
Registered: ‎01-16-2013

Re: Vivado [Place 30-675] issue

Jump to solution

@quincyq2003,

 

Thanks for the update. Can you please share the solution so that it will help other user facing the same issue. 

Also please close this thread by marking the post which helped as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
2,019 Views
Registered: ‎03-31-2016

Re: Vivado [Place 30-675] issue

Jump to solution

Hello @syedz @marcb

 

This issue is my design used 171 BUFG, so vivado can't placement complete and report this error message.

 

Reduce design BUFG can resolve this issue.

0 Kudos