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Adventurer
Adventurer
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Registered: ‎06-05-2020

Vivado RTL Implementation critical warning issue

Hello @sabankocal 

Please find the attached file of my design and also find the attached constraint file of LVDS to LVTTL conversion.

While doing implementation in vivado i am getting below critical warning.

[DRC IOSTDTYPE-1] IOStandard Type: I/O port RX_N[0] is Single-Ended but has an IOStandard of LVDS which can only support Differential

Please help me to solve to this.

Waiting for your your response.

Thank you.

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Voyager
Voyager
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Registered: ‎08-02-2019

Hi @dimpy ,

Warning is clear. You are defining a single ended pin(not differential) as differential pin and Vivado says it will not work.

To define two pins as LVDS they need to support something. For example they need to located near places...

To be sure we use mostly already differential defined pins.

Actually I shared with you everything thay you need to have.

  • You have constraints file example
  • verilog example converts LVDS to single ended
  • Then Block design example, shows how convert verilog to block design
  • similarly for outgoing signals...

As an FPGA developer you need to integrate that parts.

I could not do it instead of you because I dont know anything about your carrierboard & daugter board setup.

For example you have a carrierboard, that hat an FMC connector on it and you have attached to it an ADC eval board by using that FMC connector. Then you need to look pin list of this two boards.

  • You connected your signal as ADC input
  • You need to find which pin is coming from that ADC input to its connection point to carrier board. it is always listed in ADC's documantations. If this signal is differantial, this pins are always defined as differantial.
  • Then you need to find same pins in FMC's carrier board side pins on carrier board's pin assignment list by looking again its user guide.
  • For example: if we talk about ZC702 Xilinx eval board, then you need to look here and find this kind of related lines in this document by searching FMC LPC pin number:

 

G9 FMC1_LPC_LA03_P LVCMOS25 J20 H7 
G10 FMC1_LPC_LA03_N LVCMOS25 K21

 

This _P and _N suffixes says us these pins are differential pins and if you need you can define them also LVDS in your constraints file.

Saban

 

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