10-22-2020 10:15 PM
Please find the attached file of my design and also find the attached constraint file of LVDS to LVTTL conversion.
While doing implementation in vivado i am getting below critical warning.
[DRC IOSTDTYPE-1] IOStandard Type: I/O port RX_N is Single-Ended but has an IOStandard of LVDS which can only support Differential
Please help me to solve to this.
Waiting for your your response.
10-22-2020 11:28 PM - edited 10-22-2020 11:30 PM
Hi @dimpy ,
Warning is clear. You are defining a single ended pin(not differential) as differential pin and Vivado says it will not work.
To define two pins as LVDS they need to support something. For example they need to located near places...
To be sure we use mostly already differential defined pins.
Actually I shared with you everything thay you need to have.
As an FPGA developer you need to integrate that parts.
I could not do it instead of you because I dont know anything about your carrierboard & daugter board setup.
For example you have a carrierboard, that hat an FMC connector on it and you have attached to it an ADC eval board by using that FMC connector. Then you need to look pin list of this two boards.
G9 FMC1_LPC_LA03_P LVCMOS25 J20 H7 G10 FMC1_LPC_LA03_N LVCMOS25 K21
This _P and _N suffixes says us these pins are differential pins and if you need you can define them also LVDS in your constraints file.