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Teacher drjohnsmith
Teacher
12,206 Views
Registered: ‎07-09-2009

Vivado, USR_ACCESS and axi bus

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Using Vovado, in GUI mode, 

 

how can I set the USR_ACCESS = TIMESTAMP property ?

 

also , I would love to be able to read the USR_ACCESS from the axi bus of the zynq, 

     is there a AXi peripheral with the USR_ACCESS timestamp available , 

 

 

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado, USR_ACCESS and axi bus

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BITSTREAM.CONFIG.USR_ACCESS property is available through the "add property" dialog box of the gui so one can set it there. As to the block instantiation, I think it would be a great idea for Xilinx to make all blocks in the HDL library to be available through the IP integrator.
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado, USR_ACCESS and axi bus

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you can set the usr_access by:

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] during implementation.

As to reading it, a USR_ACCESSE2 component has to be instantiated in the design but I don't know of any IP which does this for you. It should be quite easy though.
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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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thank you

 

the company is using the vivado gui,

   can they add tcl set properties commands in the gui.

       with a tcl script mode, yes, but the problme is adding the property to the gui,

 

as for the component, 

   yes, add a gpio axi block, wire that to the User_access block, 

        again they are using the gui, so the gpio axi is in the block diagram designer, the USER_access bloxk is in native vhdl, 

  

seems a pity there is not a user-acess block in the ip integrator ,

    ,ight have to make one,, !!

 

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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado, USR_ACCESS and axi bus

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BITSTREAM.CONFIG.USR_ACCESS property is available through the "add property" dialog box of the gui so one can set it there. As to the block instantiation, I think it would be a great idea for Xilinx to make all blocks in the HDL library to be available through the IP integrator.
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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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thank you

   

will give it a go next week

 

so who do we pester to get the ip added ? or is that another story ?

 

have a good weekend

 

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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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so looking at vivado , 2013.4 make certain we have this tied down.

 

have project up, 

  

they click project Manager => Project settings 

    and on the wondow that pops up, click implimentation and scroill down to write_bitstream

 

and in the more opotions* box they add

 

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP

 

 

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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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thank you

 

customer happy with the description,

 

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Scholar dwisehart
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Registered: ‎06-23-2013

Re: Vivado, USR_ACCESS and axi bus

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This did not work for me.  Vivado 2013.4 gave me this error:

 

INFO: [Project 1-484] Checkpoint was created with build 353583
open_checkpoint: Time (s): cpu = 00:01:57 ; elapsed = 00:01:48 . Memory (MB): peak = 2307.410 ; gain = 1505.344
ERROR: [Common 17-165] Too many positional options when parsing 'TIMESTAMP', please type 'write_bitstream -help' for usage info.

while executing
"write_bitstream -force FPGA.bit set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP"
INFO: [Common 17-206] Exiting Vivado at Tue Jan 21 07:08:43 2014...

 

Daniel

 

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Teacher drjohnsmith
Teacher
12,120 Views
Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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which device are you using ?

 

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Scholar dwisehart
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Registered: ‎06-23-2013

Re: Vivado, USR_ACCESS and axi bus

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xc7vx690tffg1761-2

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Teacher muzaffer
Teacher
12,151 Views
Registered: ‎03-31-2012

Re: Vivado, USR_ACCESS and axi bus

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set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP

command should be entered at the TCL commandline before running "write_bitstream -force FPGA.bit". These are two separate actions. Also the set_property needs an object to which it applies so probably:

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
would work.
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Scholar dwisehart
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12,149 Views
Registered: ‎06-23-2013

Re: Vivado, USR_ACCESS and axi bus

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OK, the previous post said that this was to be set in Bitstream Settings->More Options, but that did not work, as noted.

 

Putting set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP in the TCL command line did work, but doing that every time before you create a bitfile in the Vivado GUI would be painful.

 

The first thing I tried that worked is putting this command in the XCF file for the project.

 

The second thing that worked was creating a TCL script file with just this command in it, and then setting Bitstream Options-> tcl.pre to this filename.

 

Thanks for the help.

Daniel

 

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Scholar dwisehart
Scholar
12,144 Views
Registered: ‎06-23-2013

Re: Vivado, USR_ACCESS and axi bus

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XDC, not UCF or XCF. My bad.
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Teacher muzaffer
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Registered: ‎03-31-2012

Re: Vivado, USR_ACCESS and axi bus

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You're welcome.
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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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what are we using for object ?

 

I've just tried typing in to tcl

 

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP

 

and I get the error 

 

ERROR: [Common 17-163] Missing value for option 'objects',

 

 

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Moderator
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12,105 Views
Registered: ‎06-05-2013

Re: Vivado, USR_ACCESS and axi bus

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Please provide default value.
For more info check page 65 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_4/ug908-vivado-programming-debugging.pdf

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Scholar dwisehart
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Registered: ‎06-23-2013

Re: Vivado, USR_ACCESS and axi bus

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open_run impl_1

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP} [get_runs impl_1]

 

 

The other option, assuming you have the implementation open:

 

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

 

Teacher drjohnsmith
Teacher
12,094 Views
Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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thank you

I think I forgot the [ ] brackets... 

 

 

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Teacher drjohnsmith
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Registered: ‎07-09-2009

Re: Vivado, USR_ACCESS and axi bus

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that worked, ta

 

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Visitor tomuon
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Registered: ‎03-18-2014

Re: Vivado, USR_ACCESS and axi bus

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For reading the timestamp, couldn't you use the AXI HWICAP controller to get at the AXSS config register?  I guess you would have to parse the bitstream during the readback.  XAPP497 seems to allude to this method. 

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