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Visitor
Visitor
2,839 Views
Registered: ‎05-09-2017

Vivado: When placing some output Pins it automatically unplaced other completely unrelated pins?

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Hallo,

 

I'm pretty new with Vivado. Experience with ISE but not with Vivado.

 

I started a new project, I assigned the pins and everything was OK. I wanted to change the assignment and out of the blue when I try to reassign some pins I got the message: "Pins X.... Y ...... are already place and will be unplaced first". This pins/ports are completed unrelated one with each other. 

For example. adc_clk1 and adc_clk0 - is the same signal connected to these two external ports (out std_logic)

  • adc_clk0 <= s_adc_clk;
  • adc_clk1 <= s_adc_clk;

When I try to connect adc_clk1 to G17 (Bank 35) vivado wants to unplace all DDR (Zynq Proc) pins from Bank 500 (or something like this).

When I try to connect adc_clk0 to G17 (Bank 35) vivado wants to unplace my LEDS(7-0) pins. 

 

I went with connecting adc_clk0. I started reconnecting again LEDS pins and at LEDS(4) now I get the same problem with completely other pins. It's like a vicious circle.

 

Please also see the attachment.

 

What am I doing wrong? Thank you!

 

Paul

adc_clk0.jpg
adc_clk1.jpg
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Visitor
Visitor
4,281 Views
Registered: ‎05-09-2017

Hi Florent,

 

You cannot see it in my pictures but I was already in the Synthesized Design (I checked it once more by 'uncropping' the screenshots attached to my post).

 

It works now. I didn't change it under I/O Ports Design (window in the lower part) but under Device Constrains/ I/O Bank 35 / G17 I assigned adc_clk_0. It worked. After a complete flow: Synthesize, Implementation & Generate Bitstream I tried again to change under I/O Ports Design and it works. 

 

Have no idea if I did something wrong??

 

Thanks,

Paul 

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Moderator
Moderator
2,818 Views
Registered: ‎11-09-2015

Hi @paul.tutzu,

 

You may want to try to change the port locations on the synthesized design (not in the implemented design).

 

Hope that helps,

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
4,282 Views
Registered: ‎05-09-2017

Hi Florent,

 

You cannot see it in my pictures but I was already in the Synthesized Design (I checked it once more by 'uncropping' the screenshots attached to my post).

 

It works now. I didn't change it under I/O Ports Design (window in the lower part) but under Device Constrains/ I/O Bank 35 / G17 I assigned adc_clk_0. It worked. After a complete flow: Synthesize, Implementation & Generate Bitstream I tried again to change under I/O Ports Design and it works. 

 

Have no idea if I did something wrong??

 

Thanks,

Paul 

View solution in original post

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Moderator
Moderator
2,809 Views
Registered: ‎11-09-2015

Hi @paul.tutzu,

 

No, I have no idea of what was the issue in your first try


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
1,326 Views
Registered: ‎12-10-2014

I'm having this exact same problem in 2018.1. When I assign a pin to a port vivado unassigns another already assigned pin which is not in conflict and I keep going around in circles.

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Contributor
Contributor
762 Views
Registered: ‎08-30-2018

I encountered the same issue, but it was because I manually entered the PACKAGE_PIN and then pressed enter. Not pressing enter was the solution.

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Observer
Observer
636 Views
Registered: ‎06-07-2019

I'm having the same problem in 2018.2. 

Is this a bug? @florentw 

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