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Visitor jeromefievet
Visitor
7,161 Views
Registered: ‎02-02-2010

Vivado - award me - faster - multi driver

Hello,

 

I am trying to compile a design which I am not able to simulate. The design is made of much copy paste, which involves possible "human errors".

 

Before I used to make synthesis with Synopsys Synplify. When there was an error of multi driver, which meant several "=> to the same signal" (in VHDL), the error was expected in 1-2 minuts... With ISE, it was also quick to establish the same error.

 

Now, for my design, all the flow of generating my binary file to be loaded to fpga is done under Vivado.

 

In Vivado, it takes one hour give me the same error.

 

The design takes about 5-6 hours to be processed. It is an issue making me loosing lot of time.

 

Here is the error:

 

ERROR: [Opt 31-37] Multi-driver net found in the design: XXXX/XXXX[0].XXXX/data_wr[0]. etc....

 

I've specialy introduced XXX for confidential matters...

 

Do someone have a work around, so that Vivado could stop in less time as did ISE or Synplify?

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4 Replies
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Visitor jeromefievet
Visitor
7,158 Views
Registered: ‎02-02-2010

Re: Vivado - award me - faster - multi driver

Thanks for answers
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7,145 Views
Registered: ‎03-27-2014

Re: Vivado - award me - faster - multi driver


@jeromefievet wrote:
I am trying to compile a design which I am not able to simulate.

why is that?

you should be able to write a test-bench either for the whole IP or the most critical part of it, it's the best way to get your debugging process started

 


jeromefievet wrote:

In Vivado, it takes one hour give me the same error.


that's the reason why we dont use implementation to test new things.

you should only implement things that have been properly tested (pre-synth. and, or post-synth simulation).

you can use the on-chip debugger afterwards, on the partial or complete implemented design.

 

don't forget that the on-chip debugger may ruin your timing performances, so remove it for any timing analysis

G.W.,
NIST - Time Frequency metrology
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Visitor jeromefievet
Visitor
7,084 Views
Registered: ‎02-02-2010

Re: Vivado - award me - faster - multi driver

Hi,

 

Thank you for your answer. I understand what you mean about that is better to debug a simulation instead of a direct implementation. It is what I do when I design or integrate an IP in which I can control easily inputs and outputs.

 

In my case, I make evolutions on a top file of a design, which gathers more than 50 instantiations of components. The design started more than 10 years ago, top design simulations were not maintened, so now it is not possible for me to spend time to start a new one.

 

I have not encountered problems until today, because ISE or Symplify was stopping synthesis very quickly in case of multi driver.

 

I would like to find a tip, so Vivado could stop in 5 minuts and not one hour.

 

Jérôme

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Xilinx Employee
Xilinx Employee
6,908 Views
Registered: ‎05-07-2015

Re: Vivado - award me - faster - multi driver

HI @jeromefievet

 

Actually, in Vivado, Multi driven nets is not report during synthesis as an Error but as a warning.(AR 64364).
CRITICAL WARNING: [Synth 8-3352].


Opt design phase will error out anyway.

However, you can  have the tool error out at synthesis phase itself by changing the severity setting of this warning.

set_msg_severity "Synth 8-3352"  "ERROR"


please refer to this AR on how to change severity setting of any message.(AR53981)
http://www.xilinx.com/support/answers/53981.html



 

Thanks
Bharath
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