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Scholar embedded
Scholar
5,723 Views
Registered: ‎06-09-2011

Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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Hi all,

I have a problem in defining Asynchronous paths in Vivado2014.4. I am using some slow signals between various clock domains - checking full and empty status of DPRAM with different clock domains - and have applied "ASYNC_REG" property for those two FFs that I used for Metastability. When I use set_clock_groups to force Vivado not checking on those paths, I receive below messages indicating that it couldn't place two FFs on the same SLICE!.. 

I can't realize why?

 

[Constraints 18-1079] Register dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.

 

By further looking into the design I see that it didn't place these FFs in the same SLICE?.

Below pictures show them.

Top.jpg

 

 

And the below one, shows 2nd FF:

Bottom.jpg

 

Below is the command I used to indicate some clocks are asynchronous:

 

set_clock_groups -name async_ADC_ETH -asynchronous \
-group [get_clocks -include_generated_clocks iADC_DCO_P] \
-group [get_clocks -include_generated_clocks iGCLKP]

set_clock_groups -name async_RXETH_TXETH -asynchronous \
-group [get_clocks -include_generated_clocks iPHY_RX_CLK] \
-group [get_clocks -include_generated_clocks iGCLKP]

 

I am wondering if I use set_false_path instead of set_clock_groups would it make Vivado enabled to apply both timing and placement constraints?

 

I appreciate any help,

Hossein

 

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Scholar embedded
Scholar
9,339 Views
Registered: ‎06-09-2011

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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Hi @avrumw,

 

Thank you for your comments. Yes, you're right. I shouldn't have used get_cells for -through because I need a net not a cell!. I changed my constraint to this format: -from&-to. In this case you have to use get_cells. However, the naming problem still existed. By chance, I learned to search it inside implemented design and found out it has been extended to something like sOverFlow_reg!.

Then I used component label and '/' before this name and saw it worked well. something like:

[get_cells ADC_Module_INST/sOverFlow_reg]

 

Thanks,

Hossein Moradi Sarvandi

 

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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@embedded dont' use set_false_path use set_max_delay -datapath_only between the q of the last flop & d of the first flop in the target clock domain. As to the issue can you show how you infer the flops?

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Historian
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Registered: ‎01-23-2009

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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The timing constraints and the ASYNC_REG do not really interfere with each other. So the fact that the tools are not packing the two synchronizer FFs into the same slice has nothing to do with the constraints...

 

The error says "constraints or mismatched control signals". The constraints it is referring to here is placement constraints (LOC or BEL constraints), not timing constraints. So unless you have LOC constraints, the problem is likely the second part - mismatched control signals.

 

In order for two flip-flops to be packed into the same slice, they must have the same control set. This means they must use the same clock, reset and ce. Since these are supposed to be synchronizers, they presumably share the same clock. Furthermore, synchronizers should always be enabled, so they probably share the same CE (which is the constant '1'). So the last one is the reset - do they both use the same reset?

 

If the ASYNC_REG flip-flops cannot be placed in the same slice (and you get this message), then the tools will place them in adjacent slices, which is what they have done (X7Y152 and X7Y153). This is not necessarily a problem - the two FFs are still close together and hence are probably fine as a synchronizer chain, but we always prefer them to be together if possible (so take a look at the control set).

 

As for the set_clock_groups - as @muzaffer mentioned, I always avoid set_clock_groups (or set_false_path between clocks, which is essentially the same thing). It is clear that you have clock crossing between the domains - if the data to be crossed is anything other than a "slow changing single bit signal with no latency requirement" then your clock domain crossing (CDC) circuit needs constraints. Using the set_clock_groups (or set_false_path between clocks) declares all paths between the domain false. Since these constraints are the highest priority, it is now impossible to constrain your CDCs.

 

Avrum

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Scholar embedded
Scholar
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Registered: ‎06-09-2011

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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Hi @muzaffer and @avrumw,

 

Thank you guys for your helpful comments. First, to @muzaffer: I searched in Vivado user guide but I couldn't find a clear example of how to use "set_max_delay" specifically for my case!. I really appreciate if you can give me some clue on this point. I don't know how to calculate "-from", "-through" and "-to" delays for such constraint?!.

 

Second, to @avrumw: You were right. This warning message had nothing to do with my timing constraint. I saw that it exists even after commenting out that constraint. Anyway, the warning says that it couldn't place those two FFs of dbg_hub module in the same SLICE!. I have used an ILA core inside my design and I do not have any control on the core properties and constraints?!. I don't know if there is a way for fixing such bugs. Helpful advice on this issue would also be highly appreciated.

 

Thank you guys,

Hossein

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Teacher muzaffer
Teacher
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Registered: ‎03-31-2012

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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@embedded -from, -to, -through are not for delays but to describe the path (ie path start from, goes through etc). You need only one delay value which is usually the period of the faster clock in your setup. The path should from the output of the last flop in the source clock domain to the input of the first flop in the target clock domain which is where you use -from and -to options. In this case you don't need the -through option.

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Scholar embedded
Scholar
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Registered: ‎06-09-2011

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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Hi @muzaffer,

 

Thank you for your answer. It's been a long time since my last post. However, I still couldn't fix the issue. I don't know why xilinx made everything so hard in Vivado. I tried various modes of set_max_delay but I always receive the same error pointing that it couldn't find that object!. Below picture shows Vivado Critical warning message in this regard:

 

Untitled.png

I have tested set_max_delay in two cases:

set_max_delay -from [get_cells ...] -to [get_cells ...] 5 -datapath_only

set_max_delay -through [get_cells ...] 5 -datapath_only

 

None of them works. I also tested both signal names between two components and component output names. But, it can't detect it. Would please give me a clue how I can find the right object?

 

Thanks in advance,

Hossein

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Historian
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Registered: ‎01-23-2009

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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I tried various modes of set_max_delay but I always receive the same error pointing that it couldn't find that object!

 

The message is telling you that it can't find the object. This doesn't (at least directly) have anything to do with the set_max_delay (so the -datapath_only flag won't make a difference).

 

It is telling you that the command

 

get_cells [sOverFlow]

 

doesn't return any objects - in other words, there is no cell named sOverFlow at this level in your design.

 

I don't know why xilinx made everything so hard in Vivado.

 

Constraints in Vivado are different - they are not necessarily hard, and Xilinx didn't make them so. The XDC format is a (very solid) implementation of the industry standard Synopsys Design Constraints (SDC). Like any new language (and XDC is a language) you can't just learn it by poking at it - if you want to use it you need to take some time to learn it. This can be done by reading the manuals - mostly UG903, or by taking a class; Xilinx, though their ATP network offers classes to teach this stuff. Take a look at this post on classes available for migrating from ISE to Vivado.

 

But back to your problem.

 

If you want to set a set_max_delay exception on clock crossing paths, then you have to identify the paths correctly. Clearly the -through [get_cells ...] you used is not the correct syntax; get_cells will return a cell - it is unusual to try and use a cell as a -through point. So what are you trying to do? Is "sOverFlow" really a "cell" or is it a net. If it is a net (which is a more common -through point), then you need to use "get_nets", not "get_cells". Specifically, you have to correctly identify the type and name of the object you want to use for the -from/-to/-through. They also need to be identified at the right level of design hierarchy...

 

If you are unsure of the object name, you should be able to find it in the schematic viewer or the hierarchy browser in the GUI (although the names should always be able to be determined directly from your RTL).

 

Avrum

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Scholar embedded
Scholar
9,340 Views
Registered: ‎06-09-2011

Re: Vivado can't apply ASYNC_REG attribute after set_clock_groups!.

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Hi @avrumw,

 

Thank you for your comments. Yes, you're right. I shouldn't have used get_cells for -through because I need a net not a cell!. I changed my constraint to this format: -from&-to. In this case you have to use get_cells. However, the naming problem still existed. By chance, I learned to search it inside implemented design and found out it has been extended to something like sOverFlow_reg!.

Then I used component label and '/' before this name and saw it worked well. something like:

[get_cells ADC_Module_INST/sOverFlow_reg]

 

Thanks,

Hossein Moradi Sarvandi

 

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