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Vivado-imported ISE-Project not working as in ISE

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Visitor
Posts: 6
Registered: ‎07-01-2016
Accepted Solution

Vivado-imported ISE-Project not working as in ISE

Hello,

 

I´m currently trying to get an old ISE-project for a Spartan6 to work on a Kintex-7 with the Vivado Software.

 

I imported it, fixed the obvious as new clock, according constraint-file and expected it to work atleast somewhat like the old implementation. 

 

But it didn´t. So after trying to fix my Code and getting no better results, i tried this: I took my project and instead of using Vivado to synthesize it for the Kintex-7 i used the ISE. And it worked as intended!

 

So now i´m very confused, why this happened. There weren´t any special timing-constraints used in ISE and so neither in Vivado, just plain standard settings.

 

From the implemented Design i can tell, that there are enormous differences in routing between these two, so i would guess, that is a part of the problem. Are there any ways to get Vivado to a more ISE-like Routing behavior? or did someone have simular problems with importing and find a solution for it?

 

Thanks in advance

 


Accepted Solutions
Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

Hello.

 

I´ve finally found the solution for my problem last week and i want to share it here, so maybe if someone has the exact problem, but i doubt it, because i think, this problem is not that common.

 

So this happened: As i said before, the project is an old one, i did not develop myself. So i took it as granted, that it was working as intended snythesized by the ISE and the code also looked valid. But i found out, that Vivado and the ISE have a different behavior in one point. This is the capabililty of synthesizing the comparation of two fixed point values.

 

The project is using the fixed_pkg_c library and it looks like, that comparison operators don´t work in ISE, but they do work in Vivado. So that is the reason, the same code (using the same libs) lead to different bahaviors. 

 

Hope it helps someone.

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Instructor
Posts: 9,052
Registered: ‎08-14-2007

Re: Vivado-imported ISE-Project not working as in ISE

The typical problem when moving from ISE to Vivado is dealing with cross-clock-domain paths.  In ISE, these paths are not timed unless the two clocks are known to be synchronous (usually because they come from the same DCM or PLL) or there is a specific timing constraint applied.  In Vivado all clocks are considered synchronous even if they come from independent external sources.  This typically leads to huge negative slack in these previously un-timed paths unless you add the appropriate timing exceptions.  That in turn causes Vivado to spend too much effort on these paths and to therefore miss timing on the intra-clock paths that should be timed as they were in ISE.

-- Gabor
Highlighted
Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

Thanks for the fast answer Gabor,

in fact, i had problems with high negative setup slack, but was able to fix this with a more polished way of getting my signals from one clock-domain to the other. And i was able to get a positive setup and hold slack in the end without getting new constraints in.

But that didn´t get my design to behave same way as it did with the ISE. And my goal is also to not change the design itself too much.

So i would rather like to understand, what they (ISE and Vivado) do differently when facing the situation, that the design generates (through IP-Core) 2 different clocks with PLL from the board clock. Because that´s what both designs do and it seems that something in Vivado get´s in trouble with routing that the way ISE did to get it functional.

And as i´m not too familiar with them yet, i would have to ask: Are there constraints i can use to get vivado work similar with these clocks as the ISE did?
Instructor
Posts: 9,052
Registered: ‎08-14-2007

Re: Vivado-imported ISE-Project not working as in ISE

Without knowing much else about your project, my other observation is that some timing constraints that you had in ISE may not have transfered to Vivado because there is no direct translation for them.  This could possibly leave some critical paths unconstrained.

 

Timing constraints in Vivado are very different than they were in ISE, so you might want to look at the user guide.  Also take a look at the Timing Constraint Wizard.  The wizard points out recommended constraints you may have left out or lost in the translation.

-- Gabor
Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

Hey Gabor,

that´s one point that confuses me. I had no timing constraints in my ISE project, so there can´t be lost that much in translation :)
But i will follow the UG on Monday and report back, if/what helped me.

In the meantime i will take a look back in here from time to time, maybe someone had the exact same problem and found a solution, i can try.

Same VHDL-Code, different Behavior in ISE and Vivado.
I´m happy about every suggestion!

Thank you all in advance.
Instructor
Posts: 9,052
Registered: ‎08-14-2007

Re: Vivado-imported ISE-Project not working as in ISE

Without any timing constraints, it's not surprising that the project can change behavior from build to build, whether in ISE or Vivado.  I would suggest going through the timing constraint wizard in Vivado and trying again.

 

Other than that, I don't see how you could find others with the "same problem" without saying how the design's behavior changed.

-- Gabor
Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

The design is stable in each of the environments, the behavior is reproducable. It just completely changes and so fails when switching from ISE to Vivado. The wizard just tells me to add some input/output delay constraints. But i don´t think that that´s my real problem.

The most remarkable difference is how the environments route the design in their repective standard settings:

ISE (PlanAhead):

ise.PNG

Vivado:

vivado.PNG

 

The behavior-change is that the design seems to fail to react on it´s inputs correctly, what leads to wrong reactions of the hardware behind the FPGA. That´s all i can say, as i do not create the design myself and am not explicitly allowed to publish it. Doesn´t help much, right? :)

 

But that shouldn´t be a problem, as i don´t seek for help regarding the design itself. What i hope to achieve is a better understanding of the difference between the environments in synthesis and routing and why this difference leads to the routing-differences seen above while they both use the same VHDL-Code on the same device and their repective standard settings.

Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

Some updates on my own researches:

 

1. Fixed all timing problems in my vivado-version and implemented all these adjustments in the ise-version of the project (where i´ve realized that they were neede there as the ise itself gave me timing fails aswell; as said, i did not code the orject myself in first place) Both Environments now have the same, timing-proven VHDL-Code.

2. So now both versions are exactly (except the possible differences in the clocking-ips of vivado/ise) the same. The used device (Genesys2-Board featuring the Kintex-7 xc7k325t-2ffg900-2) is also the same.

3. With these adjustments, the routing in ISE differs a bit in comparison to the state before my adjustments, but the difference is kind of huge anyways (the new algorithms of vivado in mind, that´s something i can accept)

 

-> Anyways. The design fails to function correctly when programming it to the device with vivado and works fine when doing it with the ISE.

ISE(PlanAhead):

ise.PNG

Vivado:
vivado.PNG

 

So i would guess, that there is some kind of Switch in Vivado that i have to pull, because i can´t accept the idea, that vivado isn´t capable of doing the same, the ise could do fine (even with the timing errors, i haven´t looked at in 1st place).

Visitor
Posts: 6
Registered: ‎07-01-2016

Re: Vivado-imported ISE-Project not working as in ISE

Hello.

 

I´ve finally found the solution for my problem last week and i want to share it here, so maybe if someone has the exact problem, but i doubt it, because i think, this problem is not that common.

 

So this happened: As i said before, the project is an old one, i did not develop myself. So i took it as granted, that it was working as intended snythesized by the ISE and the code also looked valid. But i found out, that Vivado and the ISE have a different behavior in one point. This is the capabililty of synthesizing the comparation of two fixed point values.

 

The project is using the fixed_pkg_c library and it looks like, that comparison operators don´t work in ISE, but they do work in Vivado. So that is the reason, the same code (using the same libs) lead to different bahaviors. 

 

Hope it helps someone.