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Visitor
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Registered: ‎09-14-2018

Vivado results not consistent

I am implementing a design in a spartan 7 (xc7s50csga324-1) using Vivado 2018.1.  I have a design that worked and was planning on gradually adding functionality.  However, as I did this, I was occasionally getting builds that did not work as expected in hardware.  At first, I thought it was just bugs.  As I dug into it, the problem does not seem to be related to logic - I experimented by slightly modifying the logic, removing logic, and/or adding logic - sometimes the build worked as expected considering the changes and sometimes it did not work.   As an example: I modified design to tie register A to a constant - the design worked.  I modified design to update register A when a simple control signal asserted (i.e. register write occurred) - the design did not work as expected.  I modified design to update register A based on a more complicated control signal assert (i.e. control is set after a series of events) - the design worked.

 

For the builds that did not work as expected, the broken builds all seemed to behave the same way.  There does not seem to be any correlation to the design.  I tried numerous iterations of inserting debug probes (besides sims which also did not show any issue) without any luck finding the issue.  However, one experiment I tried with odd results was when I added debug probes to a working build.  Without the probes, the build worked.  With the probes, the build did not work.  I also tried doing incremental builds but that did not seem to make any difference either. 

 

All builds have passed timing (even with the debug probes).  The design has one clock domain (100MHz).  All io paths (except for some don't cares) are constrained.  LUT utilization is only around 5%, but bram utilization is over 70%.  There are no unexpected syn or par warnings.  There are some drc errors on the brams (1839/1840 errors for async/sync resets on brams) but, as I understand it, these are not unexpected (nor can I get rid of them even though the ram control signals are reset synchronously).

 

Are there any suggestions on what can be causing these inconsistent results?  

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Moderator
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Registered: ‎01-16-2013

Re: Vivado results not consistent

@addnamehere

 

Since this is single clock domain design I believe this shouldn't be any CDC issue which is the common reason for design failing on hardware even if they met timing. 

 

I would suggest to check/fix on the drc messages related to BRAM which could be causing this issue.

Also run report_methodology and see the result. 

 

--Syed

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Visitor
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Registered: ‎09-14-2018

Re: Vivado results not consistent

Thanks for your suggestions.

 

I tried getting rid of the bram drc and that broke builds similar to all the other broken builds.

 

The methodology report did not contain any other issues other than the bram ones I already mentioned.

 

I was about to re-do all my builds again with debug probes to see if I missed something.  So, I made changes I know would break the design - which it did.  I then inserted probes and then the design worked - that was the only change - adding probes.   I then kept the probes in and made numerous changes that always broke the design before.  However, the design still worked.  I have a hard time wrapping my head around this result.  I took the probes out with all these changes and the design broke again.  I then re-added the probes and the design worked.

 

Any ideas why adding probes seems to fix everything?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Vivado results not consistent

Hi @addnamehere. Is there any more information on how the design is failing? Specifically, is there an incorrect value that can be traced upstream with the Debug Core? Is the correct data seen at the wrong time?

 

The behavior surrounding adding probes could be timing related. The difference between the two versions would mainly be placement and routing where paths would have different delays. Baselining the design would be a good way to verify the timing.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug949-vivado-design-methodology.pdf

 


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Visitor
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Registered: ‎09-14-2018

Re: Vivado results not consistent

The design is connected to a couple of led strings.  When the design fails, the leds are not lit correctly.   Interestingly, the incorrect led pattern is consistent whenever the design fails.  

 

Not sure what baselining would help with - the design is completely synchronous nor is the logic that complicated.  Check timing is good.  There are some comments about the false path constraints on the io - but those are okay.  Further, I compared datasheet reports against a working and non-working design and the io timings are identical.

 

Here is the timing summary (sorry hard to read)...

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.517 0.000 0 13695 0.015 0.000 0 13679 3.750 0.000 0 4923


All user specified timing constraints are met.

 

I agree that the issue could be related to timing, but the design is constrained so I would expect violations to be reported.  Maybe the fact that the design uses so much bram compared to luts is causing an issue?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Vivado results not consistent

Hi @addnamehere. The baselining is useful for verifying constraints correctness. Checking the functionality after each constraints addition, is a good way to narrow down which constraint is related to the problem. If a set_false_path constraint applies to logic not intended, there could be paths that should be timed, but are not.

 

I would suggest following the path of a failing LED using either debug probes or simulation back to the source of the problem.

 

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Visitor
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Registered: ‎09-14-2018

Re: Vivado results not consistent

The false path constraints are on the outputs so I do not see how that could affect internal timing - they truly are dont cares.  Other than the io, the only other constraint is for the single internal clock.  

 

I have tried simulations and I do not see anything wrong in them.

 

My current builds all work with the debug probes.  To break the design, I would have to take the debug probes out.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: Vivado results not consistent

Hi @addnamehere. Was the simulation a behavioral simulation? If so, I would try both a post-synthesis and post-route simulation to narrow down what part of the flow the design stops working. 

 

If a post-route simulation shows no problem, then this would suggest a possible timing issue.

 

You could also try a separate probing method. Probe nets not logically related to the issue, but that reside physically near the problem region. You can then verify the problem functionality in hardware, then use the replace probe functionality to replace the non-relevant probes with the problem nets. This will minimize the implementation differences seen when adding probes causes the design to suddenly work.

 

Also using a minimal number of probes and debug features has less of an impact of changing the design.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug908-vivado-programming-debugging.pdf#page=258

 


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Visitor
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Registered: ‎09-14-2018

Re: Vivado results not consistent

I ran functional, rtl simulations.  I am still trying to get the post simulations working.  The main issue with these simulations are the time frames - basically, the design performs a new function every tens of milliseconds which takes a long time to simulate.  

 

I struggle to understand the comment "a possible timing issue".   If Vivado tells me there are no failing paths and my constraints are good, then how can there be a timing issue?

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