cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
17,548 Views
Registered: ‎01-02-2019

Vivado warning: [Constraints 18-5210] No constraints selected for write.

To get used to using vivado for programming my cora z7-10, I wrote a simple program in VHDL. Everything works as it should, but I get the warning: "[Constraints 18-5210] No constraints selected for write." after the sythesis stage. I'm unable to find information on the warning (of a level I can understand, as I'm quite new to using FPGA's).

I do get a possible solution suggested by Vivado:


Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

I have set the constraints I need and they don't seem to cause problems and I don't know how I could implement what is said in the second sentence.

I'm not sure if the warning could cause unexpected behaviour. Any information or help would be greatly appriciated.

thank you in advance!

 

these lines are in my xdc file:

## PL System Clock
set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 50.000 -waveform {00.000 25.000} [get_ports { clk }];#set
 
## RGB LEDs
set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { blue }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { green }]; #IO_L16P_T2_35 Sch=led0_g
set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { red }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { debug }]; #IO_L23N_T3_35 Sch=led1_r
 
## Buttons
set_property -dict { PACKAGE_PIN D20   IOSTANDARD LVCMOS33 } [get_ports { button }]; #IO_L4N_T0_35 Sch=btn[0]
0 Kudos
42 Replies
Highlighted
Newbie
Newbie
2,367 Views
Registered: ‎08-24-2019

I am also having the same issue with Vivado 2019.1 . I have created the constraints file in the project, set it as the target, and all of my pins names have the correct case. The problem still persists.

 

Any help would be appreciated.

0 Kudos
Highlighted
Visitor
Visitor
2,269 Views
Registered: ‎09-09-2019

I had the same problem. For me it was due to a typo (due to copy-paste from tutorial) in the port name. Carefully compare to the port names used in the top entity and the xdc-file. Check your warnings in the messages tab for: [Common 17-55] 'set_property' expects at least one object. ["constraints.xdc":1]

Hope it helps.

Highlighted
Newbie
Newbie
1,978 Views
Registered: ‎10-09-2019

I have also the same problem I'm using vivado 2019.1.3 please anyone who got better idea 

0 Kudos
Highlighted
Visitor
Visitor
1,941 Views
Registered: ‎10-15-2019

Good Evening

I am using vivado 2019.1.3 . I still have the mentioned warning ([Constraints 18-5210] ) . Is there any solution for this warning ?

I am very thankfull for any help.

Repectfully

Wael Alkakhi

0 Kudos
Highlighted
Visitor
Visitor
1,836 Views
Registered: ‎10-21-2019

I as well am getting similar error in Vivado 2019.1 

I am using Zybo Zynq 7000 development board and am trying to run this tutorial:

http://blog.idv-tech.com/2014/03/22/howto-export-zynq-peripheralsi2c-spi-uart-and-etc-to-pmod-connectors-of-zedboard-using-vivado-2013-4/

I need this for IIC (I2C) for a project I am using. Any help would be appreciated.

Thanks,

Russell

0 Kudos
Highlighted
Voyager
Voyager
1,656 Views
Registered: ‎05-25-2016

I am also having the same problem running a modified zedboard example.  I'm using vivado 2019.1

0 Kudos
Xilinx Employee
Xilinx Employee
1,451 Views
Registered: ‎08-01-2019

Hi everyone,

Thanks for bringing this to our attention. There has been a CR filed for it and the message should not trigger in the upcomming release of Vivado (2020.1).

We are hoping to release an Answer Record once the behavior has been verified for the various versions. 

Thanks again!

Courtney

----------------------------------------------------------------------------------------------------------------------
Please don’t forget to reply, give kudos, and accept as a solution if you found this helpful!
----------------------------------------------------------------------------------------------------------------------

0 Kudos
Highlighted
Visitor
Visitor
1,340 Views
Registered: ‎12-11-2018

celliott wrote:

There has been a CR filed for it and the message should not trigger in the upcomming release of Vivado (2020.1).


So what should we do in the mean time? Any kind of workaround?

0 Kudos
Highlighted
Newbie
Newbie
1,159 Views
Registered: ‎10-02-2019

I don't know if this answer the problem or not.
2 days ago,i have warning,too.
Then i found i didn't Generation block design.
so i try to Generation block design.
guess what?The warning is gone.

0 Kudos
Highlighted
Visitor
Visitor
937 Views
Registered: ‎11-22-2019

I had the same issue. The problem is that this can be a very misleading error message. It seems if you have ANY errors in your constraints file, Xilinx (Vivado 2019.2) throws away the whole file and the complains you don't have a constraints file set (when in fact you think you do).

 

SOLUTION carefully check for errors in the constraints file.

0 Kudos
Highlighted
Teacher
Teacher
914 Views
Registered: ‎07-09-2009

Its a very annoying bug. That has been there for ages, as this forum witnesses.
Seems xilinx have little interest in it, imho , xilinx tend to use TCL and scripts, so don't notice this or consider it a priority.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
513 Views
Registered: ‎10-05-2019

 I got the same error message. It was working a night before. Nothing has changed. But I realized IC7, which is situtated at the center of the Basys3 board is getting so warm that you cannot even touch with your finger when the power switch is on. So I thought the board can be damaged due to some reasons. Nevertheless, I checked the pin connections of my servo and sensor, everything is connected well including vcc and ground cables.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
76 Views
Registered: ‎05-08-2012

 

Please refer to the following AR:

https://www.xilinx.com/support/answers/73510.html

As mentioned above, the message has been removed from 2020.1 as it was found confusing.

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos