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Observer
Observer
19,931 Views
Registered: ‎01-02-2019

Vivado warning: [Constraints 18-5210] No constraints selected for write.

To get used to using vivado for programming my cora z7-10, I wrote a simple program in VHDL. Everything works as it should, but I get the warning: "[Constraints 18-5210] No constraints selected for write." after the sythesis stage. I'm unable to find information on the warning (of a level I can understand, as I'm quite new to using FPGA's).

I do get a possible solution suggested by Vivado:


Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.

I have set the constraints I need and they don't seem to cause problems and I don't know how I could implement what is said in the second sentence.

I'm not sure if the warning could cause unexpected behaviour. Any information or help would be greatly appriciated.

thank you in advance!

 

these lines are in my xdc file:

## PL System Clock
set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 50.000 -waveform {00.000 25.000} [get_ports { clk }];#set
 
## RGB LEDs
set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { blue }]; #IO_L22N_T3_AD7N_35 Sch=led0_b
set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { green }]; #IO_L16P_T2_35 Sch=led0_g
set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { red }]; #IO_L21P_T3_DQS_AD14P_35 Sch=led0_r
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { debug }]; #IO_L23N_T3_35 Sch=led1_r
 
## Buttons
set_property -dict { PACKAGE_PIN D20   IOSTANDARD LVCMOS33 } [get_ports { button }]; #IO_L4N_T0_35 Sch=btn[0]
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42 Replies
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Moderator
Moderator
19,610 Views
Registered: ‎05-08-2012

Hi @pstobbe.

If you right-click on the constraints file, you should be able to select it as a "target". The following post might help.

https://forums.xilinx.com/t5/Synthesis/Remove-the-quot-target-quot-tag-from-xdc/td-p/927617


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Observer
Observer
19,593 Views
Registered: ‎01-02-2019

I've read the thread you linked. I get the same warning, but I have only one xdc file so I just set my one file as the target, but unfortunately I still get the same warning.

I've also tried creating a new project like suggested in the thread, but I still get the warning. 

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Adventurer
Adventurer
19,583 Views
Registered: ‎09-13-2018

Hi,

 

I get the same error with simple project. Also adding *.xdc and setting it as target file doesn't solve the problem.

If you encounter any solution please post :)

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Moderator
Moderator
19,568 Views
Registered: ‎05-08-2012

Hi @pstobbe.

Can the project be uploaded for review?


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Observer
Observer
19,538 Views
Registered: ‎01-02-2019

Sure thing,

All my projects have the same error, so think it won't matter which one I send. But in the interest of time I've uploaded my smallest project.

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Moderator
Moderator
19,464 Views
Registered: ‎05-08-2012

Hi @pstobbe.

Did you happen to use the File -> Project -> Archive method of creating the zip file? This is missing the XDC in question. From the log, it appears to be outside of the project directory.


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Observer
Observer
19,411 Views
Registered: ‎01-02-2019

Sorry for the slow response,

I've moved the XDC file to the foulder with the other sourcefiles (blink.srcs -> sources_1 -> new)

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Guide
Guide
19,407 Views
Registered: ‎01-23-2009

This is not the correct location (nor the correct mechanism) for constraint files.

Constraints should be added to the project "properly". There are many ways of doing this:

  • Project Manager -> Add Sources -> Add or create constraints
  • Right clicking on the Source window on the "Constraints" line and doing "Add Source"
  • use the "add_files" Tcl command

All of these (and some other) methods will add the constraint file to your project. The physical location of the constraint file can be left "outside" your project or can be copied in. If it is copied in, it will not go in sources_1, but in constrs_1/{imports or new}

But, in general, you should never be directly manipulating files under the <project> directory - these are all managed by the project manager and should only be modified through the Vivado tool.

Avrum

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Adventurer
Adventurer
19,386 Views
Registered: ‎09-13-2018

Hi,

 

I added simple script that crates very simple project, make xdc file and recreates constraints problem.

 

I use this lines to create and add properly xdc to project, but warning still occures....

# create and add xdc file to project
file mkdir $script_path/$project_name/$project_name\.srcs/constrs_1
file mkdir  $script_path/$project_name/$project_name\.srcs/constrs_1/new
close [ open  $script_path/$project_name/$project_name\.srcs/constrs_1/new/main.xdc w ]
add_files -fileset constrs_1  $script_path/$project_name/$project_name\.srcs/constrs_1/new/main.xdc
set_property target_constrs_file  $script_path/$project_name/$project_name\.srcs/constrs_1/new/main.xdc [current_fileset -constrset]

 

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Observer
Observer
19,350 Views
Registered: ‎01-02-2019

To avrumw,

That is exactly what I do with all my projects, click add sources, then add the constraints file. I simply forgot to send the XDC with the zip, so I edited the project so the constraints file would be in the source file folder, then uploaded the project

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Moderator
Moderator
19,328 Views
Registered: ‎05-08-2012

Hi @pstobbe and @blindobs.

Thanks for the additional files. The message looks to cover multiple cases. The first is that there are no constraints for the synthesis run which does not apply to the original test case. The second case is that constraints are read for synthesis, but not saved to the synthesis checkpoint <project>.runs/synth_1/<top>.dcp. In this case, the constraints are again read in during implementation. The final routed/implemented DCP would be different from the post-synthesis version, as the routed version will contain constraints.


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Highlighted
Observer
Observer
19,240 Views
Registered: ‎01-02-2019

Hi @marcb,

I think I understand what you mean, I checked if the constraints file was used for the sythesis stage and apparently it is so I'm not sure what to do.

Thank you for all the help!

Capture.PNG
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Visitor
Visitor
19,152 Views
Registered: ‎09-15-2018

Hi @pstobbe 

Can you provide your folder & drive structure ? cause it could be a read/write permition problem.

I had this problem working on distant server repo, usually, I generate a local vivado working dir to avoid this situation.

Hope it can help.

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Observer
Observer
19,145 Views
Registered: ‎01-02-2019

Hi @onsimini,

The working directory is within the project folder. The folder is in my documents, I've tried running in other folders, but I get the same warning. Thank you for the help!

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Visitor
Visitor
18,779 Views
Registered: ‎06-10-2018

I have the same warning and it is the only one. I do not know how to get rid of it. Is there already a solution?

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Observer
Observer
18,698 Views
Registered: ‎01-02-2019

hi @fub,

unfortunately I haven't, but luckily it's just a warning. I get it when using HDL wrappers of ip's like the xadc as well, but everything works as it should, so I think it might just be a bug.

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Visitor
Visitor
18,637 Views
Registered: ‎01-18-2019

Hello

I have the same issue mentioned: [Constraints 18-5210] No constraints selected for write.

The solution: "...constraints file... select it as a "target" " does not work.

In my case, I am running Vivado v2018.3 (64-bit) on Ubuntu 18.04.1 LTS 64-bit.

I am new on Vivado. I genereted the project and the surce files correctly. Actually, the synthesis, Implementation and bitstream generation works fine; even the evaluation board can be programed without problems.

I am a bit woried about this issue, it will be a drawback when generate more complex projects. Is there any solution for this?

Thanks in advance, regards from Mexico

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Moderator
Moderator
18,546 Views
Registered: ‎01-16-2013

@julio.noel

 

Can you share the archive project? 

 

--Syed

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Highlighted
Visitor
Visitor
18,345 Views
Registered: ‎06-12-2018

Hi,

 

I'm getting the exact same warning when I'm synthesizing any design.

Until a few days ago I was working with  2018.2 and everything was fine.

 

I have attached a simple project I tried to synthesize.

I'm not sure if this has to do with anything but currently I have both versions of Vivado installed.

 

Any help will be appreciated.

Regards.

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Visitor
Visitor
18,326 Views
Registered: ‎01-18-2019

Hi all

Sorry for the late reply. Attached you can found one of my projects (unfortunately all of them have the same massage).

Thanks in advance 

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Visitor
Visitor
17,572 Views
Registered: ‎03-18-2019

I also meet with the same warning, I hopethat

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Visitor
Visitor
17,570 Views
Registered: ‎03-18-2019

I hope that it can be solved soon
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Highlighted
Visitor
Visitor
17,563 Views
Registered: ‎03-18-2019

I also meet the same issure and I also worried about it
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Highlighted
Visitor
Visitor
17,252 Views
Registered: ‎10-17-2018

i have same things and after 3 hours of trying every things i found the solution

and it's funny

as you know VHDL is case insensitive, upper & lower case letters are equivalent

but Vivado Constraints some time be case insensitive and some time case sensitive , depending on your luck

To avoid the problem let Constraints pins case sensitive

Best Regard

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Visitor
Visitor
17,221 Views
Registered: ‎03-18-2019

Thank you for your help,I will try it.And later I will share you the result.
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Visitor
Visitor
17,155 Views
Registered: ‎03-26-2019

Hi,

I let my Constraints pins case sensitive but I still have the same warning.

Are you sure that the only thing you do ?

Best Regard

 

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Visitor
Visitor
17,150 Views
Registered: ‎03-18-2019

So do I.And I finally choosed to install vivado 2018.1, everything was ok. No warning and generate bitstream correctly. So I think it was just a bug.

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Newbie
Newbie
16,564 Views
Registered: ‎04-14-2019

maybe the issue is related to the vivado 2018.3

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Adventurer
Adventurer
13,922 Views
Registered: ‎09-13-2018

Any solution so far ??

This bug is also present in vivado 2019.1...

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