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Explorer
Explorer
1,648 Views
Registered: ‎03-10-2015

WARNING: [DRC RPBF-3] IO port buffering is incomplete

Hello,

I am getting

WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port ABus[0] expects both input and output buffering but the buffers are incomplete.

at the toplevel I have defind the bus as inout as shown

inout wire [42:0] ABus,

And have in the .xdc file for all the bits something like the following which set the pin and IOSTANDARD

...

set_property PACKAGE_PIN J18 [get_ports {ABus[29]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ABus[29]}]

...

What do I need to do to not see the above WARNING... I read somethwere not to set the DIRECTION override and let VIVADO to figure thing out ... so I don't set the direction override... In the top level I do read in if it is input and set to something when it is output..

Appreciate your help.

Regards, Fred

 

 

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Moderator
Moderator
1,632 Views
Registered: ‎11-04-2010

Hi, @fsahebi2014 ,

Please try to instantiate IOBUF for the inout port "ABus".

Ex:

IOBUF #(
.IS_CCIO("FALSE")
)
IOBUF_inst (
.O(O), // 1-bit output: Buffer output
.I(I), // 1-bit input: Buffer input
.IO(IO), // 1-bit inout: Buffer inout (connect directly to top-level port)
.T(T) // 1-bit input: 3-state enable input
);

 

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Explorer
Explorer
1,586 Views
Registered: ‎03-10-2015

Hello, I am not following as what you are trying to do or how your example is related to Abus?

 

Regards, Fred

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Explorer
Explorer
1,536 Views
Registered: ‎03-10-2015

@hongh 

  you asked if it resolve it ... no it didn't

 

Regads, Fred

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Moderator
Moderator
1,531 Views
Registered: ‎11-04-2010

Hi, @fsahebi2014 ,

Do you mean after instantiating the IOBUF for your Bus signal, the issue still occurs?

Could you provide a small example to show it?

 

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Explorer
Explorer
1,512 Views
Registered: ‎03-10-2015

@hongh ,

 

No I didn't know how to appy IOBUF to Abus? Can you please provide me the exact code ...

 

Regards, Fred

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Xilinx Employee
Xilinx Employee
1,467 Views
Registered: ‎04-12-2012

I guess your description of ABus connect is not for bi-direction.

You probably write connect ABus as just output or just input, don`t you?

You can check which buffer is inferred after open synthesized design.

Please check it and Please write your code more here ( connection of ABus),

 

Thanks, Takayoshi

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Moderator
Moderator
1,445 Views
Registered: ‎11-04-2010

Hi, @fsahebi2014 ,

Example code for you:

module top(
input clk,
inout [42:0] ABus,
input t,
output [42:0] ext_out,
input [42:0] in_ext
);
wire [42:0] data_in;
reg [42:0] data_out;
reg [42:0] ext_out;

 


genvar i;
generate
for (i=0; i<=42; i=i+1) begin : generate_block_identifier
IOBUF #(
.DRIVE(12), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(data_in[i]), // Buffer output
.IO(ABus[i]), // Buffer inout port (connect directly to top-level port)
.I(data_out[i]), // Buffer input
.T(t) // 3-state enable input, high=input, low=output
);
end
endgenerate

 

always @(posedge(clk))
begin
ext_out <= data_in;
data_out <= in_ext;
end
endmodule

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Explorer
Explorer
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Registered: ‎03-10-2015

@hongh,

 

You are creating the following ports which doesn't even exist in my design;

input t,
output [42:0] ext_out,
input [42:0] in_ext

I have to assigned them to some pins in .xdc, correct,  unless I don't understand what's you are trying to do....

Regards, Fred

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Teacher
Teacher
1,432 Views
Registered: ‎07-09-2009

you ask, "what we are trying to do"

   Answer  help you

 

please rember we are not paid in any way, just give our time and knowledge to help others as far as we can.

 

Did you post your source code as an attatchment ?

   did you include your xdc file ?

       did you include your test bench ?

 

If not, can you do so please and we will try to help further,

    till we have this, we are punting in the dark,

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Moderator
Moderator
1,421 Views
Registered: ‎11-04-2010

Hi, @fsahebi2014 ,

The reason why I use the below ports is just to build a completed design (Because I don't have your design) to show you how to instantiate IOBU with "generate" [providing such example is not my work, and it's general verilog knowledge]. 

You don't need to use these ports. What you need to do is only to replace your signals with the ones in the example.

input t,
output [42:0] ext_out,
input [42:0] in_ext

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