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Prasandh92
Adventurer
Adventurer
284 Views
Registered: ‎02-19-2021

WARNING: [Netlist 29-432] usage of IBUF and BUFG in UltraScale

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Can anyone help me in understanding the below warning:

WARNING: [Netlist 29-432] The IBUFG primitive 'CLK_LOC_U21_ibuf[0]' has been retargeted to an IBUF primitive only. No BUFG will be added. If a global buffer is intended, please instantiate an available global clock primitive from the current architecture.

Note: There is no IBUFG is inserted in my RTL

Then I did the below w.r.to the below link

https://forums.xilinx.com/t5/Synthesis/Synthesis-replaces-IBUFG-with-IBUF-for-clock-input/td-p/1173563

Inserted IBUF and BUFG for the clock input but still I see same warning as mentioned above?

Thanks in advance,

Prasanth S,

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hongh
Moderator
Moderator
273 Views
Registered: ‎11-04-2010

Please check the placed.dcp, if the clock structure for the clock port is (CLOCK_PORT -> IBUF > BUFG), then the warning message can be ignored.

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1 Reply
hongh
Moderator
Moderator
274 Views
Registered: ‎11-04-2010

Please check the placed.dcp, if the clock structure for the clock port is (CLOCK_PORT -> IBUF > BUFG), then the warning message can be ignored.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post