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Visitor zebras
Visitor
9,530 Views
Registered: ‎12-22-2010

WARNING:Route:466 - Unusually high hold time violation

Hi all,

 

I have a warning here that I can't fix. When this warning shows up, PAR takes extra time to try to work around it, making my implementation very time-consuming.

here is the warning message:

WARNING:Route:466 - Unusually high hold time violation detected among 324 connections. The top 20 such instances are printed below. The
   router will continue and try to fix it
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<83>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<11>:DX -3031
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<83>:BQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<11>:BX -3031
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<95>:CQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<23>:CX -3017
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<95>:BQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<23>:BX -3015
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<115>:CQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<7>:CX -3014
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<95>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<23>:AX -3014
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<95>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<23>:DX -3013
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<115>:BQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<7>:BX -3012
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<115>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<7>:AX -3011
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<115>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<7>:DX -3010
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<79>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<7>:DX -2995
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<79>:BQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<7>:BX -2995
 U_inner_logic/U_qdr_ctl0/c0_qdr_rd_adr<19>:CQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_control/iob_addr_fall0<19>:C5 -2956
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<27>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/mux_data_fall1_2r_27_BRB1:AX -2956
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<31>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/mux_data_fall1_2r_28_BRB1:AX -2955
 U_inner_logic/U_qdr_ctl0/c0_qdr_rd_adr<7>:CQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_control/iob_addr_fall0<7>:C5 -2954
 U_inner_logic/U_qdr_ctl0/c0_qdr_rd_adr<19>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_control/iob_addr_fall0<19>:A5 -2950
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<83>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_rise1<11>:AX -2950
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<111>:DQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<3>:DX -2943
 U_inner_logic/U_qdr_ctl0/c0_qdr_wr_dat<111>:AQ ->
U_qdrii_sramc/c0_u_user_top/u_qdr_phy_top/u_phy_write_top/u_phy_write_data/iob_data_fall0<3>:AX -2943

 

 

What can I do to fix this?

 

Thank you. 

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4 Replies
Xilinx Employee
Xilinx Employee
9,522 Views
Registered: ‎01-03-2008

Re: WARNING:Route:466 - Unusually high hold time violation

The instance names imply that this is part of a QDR2 controller.  Is this something you created, a Xilinx core or something that you obtained from a 3rd party?

 

After place and route, what did the timing report say about these paths?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Newbie fuzzylogic
Newbie
9,451 Views
Registered: ‎10-20-2010

Re: WARNING:Route:466 - Unusually high hold time violation

Hello, 

 

I have similar issues when implementing a DDRII SRAM controller. The board already existed so the pins are loc'ed without first implementing the code. I suspect there is a problem between placement of the pins and the BUFG's it's using... they might be on opposite halves of the chip or something, creating large routing delays?

I hope to get to work around this myself too, I'm still figuring out what is going on at this moment.

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Xilinx Employee
Xilinx Employee
9,424 Views
Registered: ‎07-01-2008

Re: WARNING:Route:466 - Unusually high hold time violation

Check for unusually high delay in the clock path. Non-optimal clock configurations will often result in "clock dedicated route" errors during clock placement. Have you bypassed any such errors? If so, go back and reread the resulting warning message.

Are all of your clocks on clock buffers? Check the Clock Report in the .par file and look for local clocks. Here's an example:

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_backplane_27M | Local| | 623 | 7.221 | 8.163 |
+---------------------+--------------+------+------+------------+-------------+


If there are no obvious issues with clock paths, then you'll need to examine the timing reports to see where the hold errors are coming from.

Explorer
Explorer
9,299 Views
Registered: ‎05-22-2008

Re: WARNING:Route:466 - Unusually high hold time violation

I have this same problem, when using the Virtex6 DSP kit reference design provided by Xilinx/AVnet for the ML605 board.

 

The components are:

 

ila0_data0<30>-> U_ila_pro_0/U0/iData

 

And things like this. ila0 are references to chipscope ila cores.

 

Has anybody else dealt with this, specfically when using the Xilinx development board and xilinx/Avnet reference design?

 

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