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Visitor
Visitor
419 Views
Registered: ‎11-02-2020

WNS is negative but Implementation Completes

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Why did Implementation complete even if there are timing violations (WNS and TNS are in red)?

 

 

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impl_7_RED.PNG
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Moderator
Moderator
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Registered: ‎11-04-2010

It just means the implementation flow is completed and bitstream can be generated, but since there are huge timing issues in the design, the bitstream cannot work properly.

It's hard for tool to resolve the unreasonable timing violation such as -1.9ns WNS automatically. Please check whether the you have handled the cross-clock domain paths correctly first.

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Moderator
Moderator
403 Views
Registered: ‎11-04-2010

It just means the implementation flow is completed and bitstream can be generated, but since there are huge timing issues in the design, the bitstream cannot work properly.

It's hard for tool to resolve the unreasonable timing violation such as -1.9ns WNS automatically. Please check whether the you have handled the cross-clock domain paths correctly first.

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Visitor
Visitor
385 Views
Registered: ‎11-02-2020

Thank you very much for the reply.

The failing path is within a single clock domain only and only has 1 level of logic. 

Attached is a snippet of the report.

 

Any thoughts?

path341.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @uxxexzer 

using this please generate a text timing report of the failing path and share it with us.

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Visitor
Visitor
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Registered: ‎11-02-2020
Hi @surajc,
We need to fix the RTL to infer BRAMs instead of FDCE.
Thanks.