11-02-2020 05:19 PM - edited 11-02-2020 07:34 PM
Why did Implementation complete even if there are timing violations (WNS and TNS are in red)?
11-02-2020 05:48 PM
It just means the implementation flow is completed and bitstream can be generated, but since there are huge timing issues in the design, the bitstream cannot work properly.
It's hard for tool to resolve the unreasonable timing violation such as -1.9ns WNS automatically. Please check whether the you have handled the cross-clock domain paths correctly first.
11-02-2020 05:48 PM
It just means the implementation flow is completed and bitstream can be generated, but since there are huge timing issues in the design, the bitstream cannot work properly.
It's hard for tool to resolve the unreasonable timing violation such as -1.9ns WNS automatically. Please check whether the you have handled the cross-clock domain paths correctly first.
11-02-2020 07:47 PM
Thank you very much for the reply.
The failing path is within a single clock domain only and only has 1 level of logic.
Attached is a snippet of the report.
Any thoughts?
11-03-2020 02:45 AM
11-08-2020 04:33 AM