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Explorer
Explorer
1,150 Views
Registered: ‎05-16-2014

What are maximum PAR options?

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If one has a large design what PAR options tells the software tool to exhaust everything possible? 

-ol HIGH  -xe c

 

That is, if the FPGA design doesn't PAR with those two options then you're finished. The design, with the current constraints, won't work. 

 

I am running into such an issue. I'm using those two options above. Is there another option that can be added?

 

Thanks

 

 

 

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Historian
Historian
1,706 Views
Registered: ‎01-23-2009

Re: What are maximum PAR options?

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Did the PAR exhaust every possible route with the options I stated above or are there other options I can add,

 

I'm not sure what you mean. Are you saying "are there other options that might success where this has failed"? If so, then yes, there are. You can consider Multi-pass place and route, and other implementation strategies. That being said, the options you used will never "fail" - the -xe c means "never stop" - so if it cannot meet timing it will run forever.

 

If you are asking if this option will "exhaust all possible routing solutions" (i.e. try all possible combinations of placement and routing), then absolutely not. It is very easy to prove that an "exhaustive" search of the solution space (even for a relatively small FPGA) takes more compute time than the time the universe has existed (by a LOT!).

 

But a parts of you message don't make sense... You say the failures are in DDR memory signals - do you mean "on signals in the DDR controller" or the actual memory signals (going out of the FPGA) themselves. If it is the latter, then the pass/fail of these are determined purely by the constraints, since these are (or at least absolutely should be) using the IOB flip-flops, whose timing are not impacted by placement or routing. If they are in the memory controller (i.e. the MIG) then you are seeing normal timing failures due to placement and/or the "chaotic" nature of FPGA implementation.

 

Avrum

 

 

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3 Replies
Moderator
Moderator
1,130 Views
Registered: ‎09-15-2016

Re: What are maximum PAR options?

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@swimteam

 

What exactly  the issue you are facing? When you say design with constraints doesn't work, are there any warnings?

You can refer below link, Chapter 9, page 123 onwards:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/devref.pdf

 

Regards

Rohit

 

 

Regards
Rohit
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Explorer
Explorer
1,098 Views
Registered: ‎05-16-2014

Re: What are maximum PAR options?

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The ISE PAR completes, but our script files do checks for errors. It reports that there are some DDR memory signals that are not meeting timing. If I remove some code then the timing is met . This code has nothing to do with the DDR. That's why I asked the question: Did the PAR exhaust every possible route with the options I stated above or are there other options I can add, The code added is rather small (10 or 20 lines).

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Historian
Historian
1,707 Views
Registered: ‎01-23-2009

Re: What are maximum PAR options?

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Did the PAR exhaust every possible route with the options I stated above or are there other options I can add,

 

I'm not sure what you mean. Are you saying "are there other options that might success where this has failed"? If so, then yes, there are. You can consider Multi-pass place and route, and other implementation strategies. That being said, the options you used will never "fail" - the -xe c means "never stop" - so if it cannot meet timing it will run forever.

 

If you are asking if this option will "exhaust all possible routing solutions" (i.e. try all possible combinations of placement and routing), then absolutely not. It is very easy to prove that an "exhaustive" search of the solution space (even for a relatively small FPGA) takes more compute time than the time the universe has existed (by a LOT!).

 

But a parts of you message don't make sense... You say the failures are in DDR memory signals - do you mean "on signals in the DDR controller" or the actual memory signals (going out of the FPGA) themselves. If it is the latter, then the pass/fail of these are determined purely by the constraints, since these are (or at least absolutely should be) using the IOB flip-flops, whose timing are not impacted by placement or routing. If they are in the memory controller (i.e. the MIG) then you are seeing normal timing failures due to placement and/or the "chaotic" nature of FPGA implementation.

 

Avrum

 

 

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