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Anonymous
Not applicable
4,377 Views

When Virtex5 adds some outputs to another Virtex5, the result goes wrong

Hi,

      We use Virtex5 to compress image data, and our design is like this: a first Virtex5(V1) receive data from sending board, do the comprssion and also transfer the original data to another Virtex5(V2) and the V2 do the compression too.

The V1 can always have the right result without the outputs to V2 but it goes wrong if it has the outputs to V2.

    So what would the potential reasons for this problem?

 

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3 Replies
awillen
Mentor
Mentor
4,368 Views
Registered: ‎11-29-2007

How should we know? You give us hardly any information, and your question is confusing. Be more specific and post more details.



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
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bassman59
Historian
Historian
4,344 Views
Registered: ‎02-25-2008

 


@Anonymous wrote:

Hi,

      We use Virtex5 to compress image data, and our design is like this: a first Virtex5(V1) receive data from sending board, do the comprssion and also transfer the original data to another Virtex5(V2) and the V2 do the compression too.

The V1 can always have the right result without the outputs to V2 but it goes wrong if it has the outputs to V2.

    So what would the potential reasons for this problem?

 


Your design is screwed up.
Did you bother to simulate the entire board design, including both FPGAs, the source stimulus and the output data sink? If not, then your design hasn't been verified and debugging in-circuit as you are doing is a waste of time.

 

----------------------------Yes, I do this for a living.
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brucey
Xilinx Employee
Xilinx Employee
4,260 Views
Registered: ‎03-24-2010

Hi, you can do timing analysis for input and output signals. Besides, you can also do timing simulation to find where the issue is.

Regards,
brucey
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