10-04-2017 08:45 AM
Im new to the Vivado tool flow after coming from an Altera Quartus background. Im using Vivado 2017.2.
Im trying to figure out why the place and route (implementation) stage has optimized away a bunch of logic that is still present after the synthesis stage. Ive searched the implementation log within the GUI for the name of the design object that has disappeared but nothing is listed.
Im looking in the .runs/impl_1 folder but a log file isnt jumping out at me.
And pointers would be appreciated!
10-04-2017 09:02 AM
In the run folder:
Or you can also see the full vivado.log file which is generated at the location from where you have launched vivado (just type pwd in the tcl console to know this location).
10-04-2017 09:12 AM - edited 10-04-2017 09:16 AM
In the Implementation setting, set "-verbose" switch in more options as shown below for each implementation stage which is enabled or on by default (opt_design, place_design, route_design) to get the detailed report.
Once the switch is set, you will see the detailed report in runme.log file which will be present in <project>/<project>.runs/impl_1 folder.
Also check Chapter 2 in below Implementation user guide to know the complete Vivado implementation flow: