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Visitor b_3
Visitor
223 Views
Registered: ‎12-02-2019

Why is LOC and IOSTANDARD required for this port?

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Starting with a really simple block design, but generate bitstream is failing because I have not defined a LOC and IOSTANDARD for "ps_clk_p".  Any ideas why they are required for this port/net which does not route to an external pin?  I must be doing something wrong here.

image.png

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 2 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ps_clk_p.
ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 2 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ps_clk_p.

Looked at a bunch of posts and ARs, like this one:

https://www.xilinx.com/support/answers/56354.html

Still don't understand why this is being flagged when it is internal?  I would prefer not to downgrade the error.

Port definion in rtl:

entity fan_test is
port (     ps_clk_p : in std_logic;     fan_en : out std_logic;     fan_tach : in std_logic   ); end fan_test;

xdc for other two ports which do map to pins:

set_property PACKAGE_PIN AG14 [get_ports "fan_en"] ;# Bank 24 - IO_L2P_AD14P_24
set_property IOSTANDARD LVCMOS33 [get_ports "fan_en"]
set_property DRIVE 4 [get_ports "fan_en"]
set_property SLEW SLOW [get_ports "fan_en"]
set_property PULLTYPE {} [get_ports "fan_en"]

set_property PACKAGE_PIN AH14 [get_ports "fan_tach"] ;# Bank 24 - IO_L2N_AD14N_24
set_property IOSTANDARD LVCMOS33 [get_ports "fan_tach"]
set_property PULLTYPE PULLUP [get_ports "fan_tach"]

Thanks!

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1 Solution

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Moderator
Moderator
66 Views
Registered: ‎04-24-2013

Re: Why is LOC and IOSTANDARD required for this port?

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Hi @b_3 ,

Would it by any chance be defined in the block design wrapper, perhaps this file is out of date.

If you delete it from the project and regenerate it then you might not see the issue, you could also try reseting the output products and generating them again just to make sure that everything is clean.

Best Regards
Aidan

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6 Replies
200 Views
Registered: ‎06-21-2017

Re: Why is LOC and IOSTANDARD required for this port?

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Does the schematic of the implemented design show the ps_clk_p coming from the Zynq PS or from a pin?  This is just a guess, but Vivado likes to assume things based on signal names.  If you remove the "_p" from the fan_test IP port name, does your problem disappear?

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191 Views
Registered: ‎06-21-2017

Re: Why is LOC and IOSTANDARD required for this port?

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Also, if you have a clock wizard inside the IP block, make sure that is clock input selection is not a clock capable pin.

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Visitor b_3
Visitor
182 Views
Registered: ‎12-02-2019

Re: Why is LOC and IOSTANDARD required for this port?

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It's coming from the PS as one of the " PL Fabric Clocks".  I tried a few port names in the rtl with the same result:

clk, pl_clk0, ps_clk, ps_clk_p

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Visitor b_3
Visitor
180 Views
Registered: ‎12-02-2019

Re: Why is LOC and IOSTANDARD required for this port?

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The pl_clk0 port setup is in the PS block configuration and is using the PS dedicated clock input pin as the source.  I think this part is all still in the default configuration.

image.png

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Moderator
Moderator
67 Views
Registered: ‎04-24-2013

Re: Why is LOC and IOSTANDARD required for this port?

Jump to solution

Hi @b_3 ,

Would it by any chance be defined in the block design wrapper, perhaps this file is out of date.

If you delete it from the project and regenerate it then you might not see the issue, you could also try reseting the output products and generating them again just to make sure that everything is clean.

Best Regards
Aidan

------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if this answered your question
Give Kudos to a post which you think is helpful and may help other users
------------------------------------------------------------------------------------------------------------------

View solution in original post

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Visitor b_3
Visitor
53 Views
Registered: ‎12-02-2019

Re: Why is LOC and IOSTANDARD required for this port?

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Thanks Aidan.  Looks like it was something in the wrapper.  Regenerated it and the bitstream generated just fine.

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