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hoosha
Adventurer
Adventurer
10,465 Views
Registered: ‎02-29-2008

Why lock_pins constraint is not working using VHDL in ISE 11.3?

I am trying to use lock_pins constraint on a LUT6_2 primitive in Virtex-5. I have used the constraint in this way:

 

attribute lock_pins: string;

attribute lock_pins of LUTMUX0: label is "all";

 

but it is not working. the design tool keeps optimizing it by deleting and moving the signals around. How can I use lock_pins constraint. Do I need any synth or implementation options for this to work?

 

Thanks,

Hooman

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12 Replies
10,455 Views
Registered: ‎07-15-2008

Hi Hooman

 

does this help ? http://www.xilinx.com/itp/xilinx7/books/data/docs/cgd/cgd0115_76.html

 

Kind Regards Bobster

 

 

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hoosha
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Registered: ‎02-29-2008

No, not actually. It is a bit old (ISE V7.1) and I checkd the new version of the document and according to that document it must work. but it doesn't work on ISE 10 and ISE 11.3. I guess there is a synth or implementation optioin that needs to be turned on or off to let this happen but I don't know which one.

 

check the attached vhdl file. if you implement this on ISE v11.3 the lut pins are not locked and the BEL constraint doesn't work as well.

 

Can someone help?

 

Thanks,

Hooman 

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ywu
Xilinx Employee
Xilinx Employee
10,437 Views
Registered: ‎11-28-2007

Other than one compile error in your test case, the LOCK_PINS constraint seems to work fine (see the snapshot of the LUTinst in FPGA_EDITOR).

 

Cheers,

Jim

 

 

Cheers,
Jim
ScreenHunter_02 Oct. 23 09.55.gif
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hoosha
Adventurer
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10,435 Views
Registered: ‎02-29-2008

That's only by chance. But you can see in your snapshot that it is not A6LUT but a D6LUT. So the BEL constraint is not working. The lock_pins sometimes work but it depends on the situation I guess.

for example put INIT => X"0000000000000001" in line 145 and see what happens to the last input (in my case).

 

And lock_pins does not stop ISE from optimizing LUT out. for example put INIT => X"0000000000000000" in line 145 and see how the whole LUT is optimised out regardless of the lock_pins.

 

It is particularly confusing because the same code works fine in v9.2i.

 

Thanks,

Hooman

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ywu
Xilinx Employee
Xilinx Employee
10,405 Views
Registered: ‎11-28-2007

Sorry, I didn't realize the problem with the BEL constraint. Looks like ISE 10/11 changed the optimization on LUT6_2. To get everything to work, you will need to use the LOCK_PINS and SAVE NET FLAG on the inputs to the LUT. The reason the code below uses a temporary singal for the inport is because the S constraint can't be added directly to IO pads. Check this blog to see the complete Verilog and VHDL examples and additional notes 

 

 

attribute S: string;
attribute S of inport_tmp : signal is "true";

begin

inport_tmp <= inport;

LUTinst: LUT6_2   
        generic map (
            --INIT => X"0000000100000001"
            INIT => X"0000000000000001"
            )
        port map (                   
            O6 => ledport(1),  -- 6/5-LUT output (1-bit)
            O5 => ledport(0),  -- 5-LUT output (1-bit)               
            I0 => inport_tmp(0),   -- LUT input (1-bit)   
            I1 => inport_tmp(1),   -- LUT input (1-bit)
            I2 => inport_tmp(2),   -- LUT input (1-bit)
            I3 => inport_tmp(3),   -- LUT input (1-bit)
            I4 => inport_tmp(4),   -- LUT input (1-bit)
            I5 => '1'    -- LUT input (1-bit)
        );

Cheers,
Jim
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hoosha
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Registered: ‎02-29-2008

thanks for the reply. but I still have problems. Now, I get this warning and end up with the input signals not routed:

 

WARNING:Par:288 - The signal inport_temp<0> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal inport_temp<1> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal inport_temp<2> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal inport_temp<3> has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal inport_temp<4> has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

 

I have attached the vhdl code I am using to test this.

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ywu
Xilinx Employee
Xilinx Employee
10,368 Views
Registered: ‎11-28-2007

Does the S attribute at least work for all non-zero INIT strings? For the case INIT=all 0's, I guess there is no way to prevent the tool from optimizing out a LUT that absolutely does nothing (at least I can't think of any use). Can you explain why you want to do this (i.e. set INIT=all 0's)?

 

Cheers,

Jim

 

Cheers,
Jim
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ywu
Xilinx Employee
Xilinx Employee
10,366 Views
Registered: ‎11-28-2007

Probably it won't work when INIT=all 1's either.

 

Cheers,

Jim

Cheers,
Jim
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hoosha
Adventurer
Adventurer
10,364 Views
Registered: ‎02-29-2008

Yes that' sthe effect of constant trimming:

 

http://www.xilinx.com/support/answers/23990.htm

 

I want to reconfigure this LUT using ICAP later. but the initial content I need for the LUT in my real application is not all 0s. the init in my real application makes some inputs redundant and those inputs are trimmed!

 

I guess  I have to use "00...00001" and then reconfig to the default value before starting my system clock.

 

what do you think?

Hooman

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ywu
Xilinx Employee
Xilinx Employee
6,371 Views
Registered: ‎11-28-2007

Looks like you're working on a cool project. If setting INIT to "00...00001" is what it takes to get what you want, go for it.

 

Cheers,

Jim

 

Cheers,
Jim
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mehrdadfeller
Visitor
Visitor
5,883 Views
Registered: ‎05-17-2008

Hi guys,

 

I have almost the same problem. I am implementing a non-conventional circuit as follows (I am measuring LUT internal delays for different inputs..some I need this to work):

 

I am instantiating an LUT that implements a buffer Out=A1. The function of the LUT is not dependent on other LUT inputs. In other words,the rest of the inputs are don't cares, but I would like to keep them in my design. Here is my module:

 

-------------------------------------

module control(A1,Out, T);

 

input A1, T;

output Out;

 

LUT6 #(
.INIT(64'haaaaaaaaaaaaaaaa) // This implement a buffer hex a=binary 1010
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);

 

endmodule

-------------------------------------

 

The rest of the inputs are being connected to each other (net "t") and controlled by another logic gate.

 

In my UCF file, I specify the following location constaint:

INST "LUT6_inst" LOC = "SLICE_X17Y27";

 

Now when the design is synthesize, I see the LUT in the RTL/Technology schematic the way I want...but what comes after MAP and PAR does not include the "T" net, which is apparently optimized out. In other word, the physical design view on FPGA editor is the LUT with only one input (A1), and there is no sign of the net "T".

 

More weired is that in the MAP report there is nothing any nets being removed...!

 

I searched a little bit and added the following MAP/Synthesis constaints but the problems still persists:

 

-------------------------------------

module control(A1,Out, T);

 

(* KEEP = "TRUE" *) (* S = "TRUE" *) input A1, T;

(* KEEP = "TRUE" *) (* S = "TRUE" *) output Out;

 

(* LOCK_PINS = "all" *) LUT6 #(

.INIT(64'haaaaaaaaaaaaaaaa) // Specify LUT Contents
) LUT6_inst (
.O(Out), // LUT general output
.I0(A1), // LUT input
.I1(T), // LUT input
.I2(T), // LUT input
.I3(T), // LUT input
.I4(T), // LUT input
.I5(T) // LUT input
);

 

endmodule

-------------------------------------

 

I also tried adding the following to the UCF file instead of the verilog source to no avail.

NET "T" KEEP;

NET "T" S;

 

I get the following message:

 

WARNING:Par:288 - The signal T_IBUF has no load.  PAR will not attempt to route this signal.

 

and when i look in FPGA editot there is the LUT with only one input being used!

 

BTW, I am using Xilinx ISE Pack 11.4.

 

I would really appreciate your Help!

Thanks,

Mehrdad

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ywu
Xilinx Employee
Xilinx Employee
5,846 Views
Registered: ‎11-28-2007

If you're doing something similar to what hoosha is doing, then choose a INIT string that will keep all inputs and then change the INIT string later.

Cheers,
Jim
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