08-19-2020 10:22 PM
One net delay is 5ns in my critical path .
But the net have only one fanout.
and it is very short net.
Why does it have so long delay
Thank you
08-19-2020 10:30 PM
HI @khyu
1. Can you check the hold requirement of this path?
2. Is there any local congestion around the area where the flop and lut are placed? ( to check if the tool is trying to avoid the congestion and thus the large delay )
3. Did you try different placer and router directives ?
08-19-2020 11:18 PM
1. Can you check the hold requirement of this path?
The hold slack is 3.541
2. Is there any local congestion around the area where the flop and lut are placed? ( to check if the tool is trying to avoid the congestion and thus the large delay )
There is no congestion in these two CLB
3. Did you try different placer and router directives ?
I use the Performance_ExplorePostRoutePhysOpt
Which strategy do you suggestion?
08-19-2020 11:33 PM
08-20-2020 12:05 AM
Hi Surajc:
My hold requirement is 0
08-25-2020 01:49 AM
Hi @khyu
Can you share the post opt dcp with me?
Let me know so that I can send an ezmove link for securely sharing the design
08-25-2020 06:28 PM
Hi Surajc:
Yes , I can share the post route opt dcp file
You can send me the upload link
08-28-2020 01:26 AM
HI @khyu
I checked your design and there are a lot of critical warnings in methodology report.
Please try fixing those and then proceed for implementation.
08-28-2020 02:09 AM
Hi Surajc:
Thank you .
I will clear the critical warning and try again
09-02-2020 03:45 PM
If it doesn't violate timing constraints, perhaps the router thought the bits would just like to take the scenic route around the chip? Go on a lazy Sunday drive around the [IP] block?