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Observer eita
Observer
5,508 Views
Registered: ‎12-21-2017

Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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Hi, everyone.

 

When I finished implimentation, critical warning occures.
How to solve this?

 

I'm trying to use UltraScale+ PCI Express Integrated Block(1.3).
I connected all user logic to PCI Express Integrated Block, and also connected PCI Express External ports.
Critical warning massage is


"[Vivado 12-1411] Cannot set LOC property of ports, Instance 
U_pcieip/...pcie4_uscale_plus_0.../gthe4_channel_gen.gen_gthe4_channel_inst[3].GTHE4_CHANNEL_PRIM_INST
can not be placed in GTHE4_CHANNEL of site GTHE4_CHANNEL_X0Y12 because the bel is occupied by 
U_pcieip/...pcie4_uscale_plus_0.../gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST(port:). 
This could be caused by bel constraint conflict ["io.xdc":439]"

 

Same warning are occures on other PCIe RX ports.

 

MY .xdc constraints below.
set_property PACKAGE_PIN Y2 [get_ports RX0_P]
set_property PACKAGE_PIN W4 [get_ports RX1_P]
set_property PACKAGE_PIN V2 [get_ports RX2_P]
set_property PACKAGE_PIN U4 [get_ports RX3_P]

 

Device pin function is below.
Y2  MGTHRXP0
W4 MGTHRXP1
V2  MGTHRXP2
U4  MGTHRXP3

 

I think my constraint are correct to use PCIe,
But the warning message means these ports is occupied by other PCIe ports.
And then, open implementation design and see I/O ports,pin assignment are change.

 

.xdc        -> Implemanted design
RX0(Y2) -> RX0(U4)
RX1(W4) -> RX1(W4)
RX2(V2) -> RX2(V2)
RX3(U4) -> RX3(Y2)

 

Tool Version: Vivado v2017.3

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Xilinx Employee
Xilinx Employee
7,218 Views
Registered: ‎08-01-2008

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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This issue can occur due to incorrect use of IBUFDS_GTE2 for MRCCs. 

When differential clocks are coming from MRCCs or SRCCs, IBUFGDS/IBUFDS should be used, not an IBUFDS_GTE2. 

The problem can be resolved by replacing the IBUFDS_GTE2 with an IBUFGDS/IBUFDS.

 

check this ARs as well if you using IPI flow 

Thanks and Regards
Balkrishan
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6 Replies
Xilinx Employee
Xilinx Employee
7,219 Views
Registered: ‎08-01-2008

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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This issue can occur due to incorrect use of IBUFDS_GTE2 for MRCCs. 

When differential clocks are coming from MRCCs or SRCCs, IBUFGDS/IBUFDS should be used, not an IBUFDS_GTE2. 

The problem can be resolved by replacing the IBUFDS_GTE2 with an IBUFGDS/IBUFDS.

 

check this ARs as well if you using IPI flow 

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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Observer eita
Observer
5,489 Views
Registered: ‎12-21-2017

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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Hi Balkrishan.

 

Thanks for reply.

 

I use IBUFDS instead of IBUFDS_GTH4, then critical warning has been resolved.

But my project is using Ultrascale+ FPGA, then reference clock of PCIe is instantiated on IBUFDS_GTH4.

 

UG578 p.24
https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf

 

After change to IBUFDS, new Critical Warning become on PCIe reference clock port.

 

[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements:
CLK_P
U_RefClk/IBUFCTRL_INST
CLK_N
U_RefClk/DIFFINBUF_INST
["/home/eita/project/VIVADO/const/io.xdc":438]

 

So, I think reference clock must use IBUFDS_GTH4.

I'll try to change reference clock port assigns.

 

Regards.

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Observer eita
Observer
5,260 Views
Registered: ‎12-21-2017

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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Hi Balkrishan.

 

It's solved.

 

When I use UltraScale+ PCI Express Integrated Block(1.3), the IP Block generate xdc for pin assign.

Vivado refer this xdc file by the default, so location conflict occuers on user xdc.

 

Way to solve this issue, set an empty location before the user location constraint in xdc below.

 

 

set_property PACKAGE_PIN {} [get_ports RX0_P]
set_property PACKAGE_PIN {} [get_ports RX1_P]
set_property PACKAGE_PIN {} [get_ports RX2_P]
set_property PACKAGE_PIN {} [get_ports RX3_P]
set_property PACKAGE_PIN Y2 [get_ports RX0_P]
set_property PACKAGE_PIN W4 [get_ports RX1_P]
set_property PACKAGE_PIN V2 [get_ports RX2_P]
set_property PACKAGE_PIN U4 [get_ports RX3_P]

Regards.

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Explorer
Explorer
4,438 Views
Registered: ‎08-31-2016

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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Hi,

 

I'm facing a similar issue and trying out your @eita solution. Can anyone tell me how does setting an empty location before will help?

 

What is it going to do?

 

Regards,

Vinay

Vinay Shenoy
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Visitor rileybaird
Visitor
2,684 Views
Registered: ‎08-08-2018

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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I am also looking for a solution to this exact problem. I am not even using the PCIE core, but simply the IBERT for GTH transceivers core, and it causes the same error.

The default .xdc file made with the IBERT core appears to set the location here:

set_property LOC GTHE4_CHANNEL_X0Y12 [get_cells QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel]

But it is a read-only file so it is not changeable. 

I tried the solution of setting the nets to blank ports but it didn't work.

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Moderator
Moderator
2,674 Views
Registered: ‎11-04-2010

Re: Why "[Vivado 12-1411] Cannot set LOC property of ports" warning occuers on PCIe ports?

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Hi, @rileybaird ,

Please create a new thread for the new question. If necessary, you can add the link of the original post.
Attaching a new question to a thread that has been marked as answered will have less a chance of being found.
Thank you for your cooperation and understanding.

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