07-24-2020 09:14 PM
07-25-2020 01:02 AM
In the attached log file, I see phys_opt_design did complete successfully and also the dcp file was generated without any error.
phys_opt_design completed successfully
phys_opt_design: Time (s): cpu = 00:13:07 ; elapsed = 00:05:17 . Memory (MB): peak = 6387.844 ; gain = 0.000 ; free physical = 357684 ; free virtual = 363648
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:17 ; elapsed = 00:00:06 . Memory (MB): peak = 6387.844 ; gain = 0.000 ; free physical = 357544 ; free virtual = 363620
INFO: [Common 17-1381] The checkpoint '/home/ittmp1/khyu/fpga/aab033_khyu/VU440_FPGA16_IOB_r285_dram_nc_slr_6ns/aab033/aab033.runs/impl_2/aab033_physopt.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:30 ; elapsed = 00:00:22 . Memory (MB): peak = 6387.844 ; gain = 0.000 ; free physical = 357086 ; free virtual = 363081
I believe you must have right-clicked on "Run Implementation" and selected option to run till post place phys_opt_design hence route_design did not run. To run complete implementation flow left-click on "Run implementation" or select "Generate Bitstream"