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Scholar dpaul24
Scholar
3,861 Views
Registered: ‎08-07-2014

Why this Warning message during "Route-Design" process

Hi,

 

I am using the part xc7a200tifbv676-1L (Artix7) in a design. I am using Vivado 2017.1.

During 'Route-Design' stage I get the warning...
.
.
Finished Running Vector-less Activity Propagation
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
.
.

In the log Messages window it is displayed as:
[Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.


These following constraints (among others) are in my xdc file, but I don't understand which one can be responsible.

set_property INTERNAL_VREF  0.750    [get_iobanks 12]
set_property INTERNAL_VREF  0.750    [get_iobanks 14]
set_property IOSTANDARD LVCMOS33  [ get_ports {slot*}        
set_property IOSTANDARD LVCMOS15  [ get_ports {a7_rsvd*   }]
set_property IOSTANDARD LVCMOS33  [ get_ports {a7_phy_* } ]
set_property IOSTANDARD LVCMOS15  [ get_ports {sf2_a7_*  } ]

set_property CONFIG_VOLTAGE  1.5   [current_design]
set_property CFGBVS                  GND   [current_design]

 


Can anyone throw some light on this?

 

Thanks.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
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4 Replies
Xilinx Employee
Xilinx Employee
3,805 Views
Registered: ‎07-16-2008

Re: Why this Warning message during "Route-Design" process

It's most likely a tool issue in 2017.1. There is no VCCINTIO for 7 Series.

A CR has been submitted to dev team for investigation. Please ignore the warning.

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Scholar dpaul24
Scholar
3,796 Views
Registered: ‎08-07-2014

Re: Why this Warning message during "Route-Design" process

Thanks for the reply.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Visitor asharapov
Visitor
3,251 Views
Registered: ‎01-31-2013

Re: Why this Warning message during "Route-Design" process

Same problem in Vivado 2017.2

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Xilinx Employee
Xilinx Employee
2,665 Views
Registered: ‎11-08-2013

Re: Why this Warning message during "Route-Design" process

This issue will be fixed in the 2017.3  Vivado release.

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