02-06-2018 03:05 PM - edited 02-06-2018 03:06 PM
Reminds me of a physics joke, but I will pass on that.
One way is to sum all the delays for all interconnect. The delay is from the wire's length (speed of light in silicon is half that of in air on a transmission line), plus any buffer delay.
Another way is to look at the dynamic power of the routing, knowing FCV^2 = P, one can estimate C, and then guess at the wire dimensions, solving for a Cwire.
Or, you could read up on the interconnect resources, look at the implemented design cartoons and estimate wire length from the displayed routing.
So, I am sure you can get within a factor of 3:1:1/3 based on the above.
The question is why?
(The joke is how can you use a barometer to find the height of a building....):