09-04-2019 11:45 AM
I am using vivado 2018.1 version, running experiment on our IP design.
After implemenation, I'd like to wrtie a verilog netlist to compare with netlist I exported after synthesis.
what is the correct command?
09-12-2019 03:37 PM
If the post from miker was helpful, can you mark this as a accepted solution? This would help others who are looking for the same information. If not, please update the thread with any clarifications.
09-12-2019 03:48 PM
I still have question about synthesis and implemenation.
After synthesis, I have a timing vioaltion about -2.45ns in one clock domain (phy_clk is a primary input port), I wrote out the netlist wiht write_verilog -mode design syn_netlist.v
After running implmenation, when running timing summary, I could not find the clock paths in phy_clk domain any more. When written in netlist with write_verilog, the netlist shows no IBUF instantiated, and the phy_clk goes to lower level modules becomes unconnected. What might cause the discrepency between synthesis and implmenation. the constraints used for both are the same.
09-17-2019 03:05 PM
Pease start a new post as this is a new topic.