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Scholar ronnywebers
Scholar
1,873 Views
Registered: ‎10-10-2014

XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

Using VIvado 2017.2

 

I created a custom IP containing an XPM_FIFO_SYNC macro. My custom IP simulates, fifo works fine, ...

 

I used the language template to instantiate the XPM_FIFO_SYNC, and instantiated it in a 'wrapper' vhdl file that simplifies the fifo interface a bit :

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Xilinx component used : XPM_FIFO_SYNC
Library xpm;
use xpm.vcomponents.all;

entity rx_fifo is
port (
rst : in std_logic;
clk : in std_logic; -- sync FIFO, only clk domain

enable : in std_logic; -- wr_en is ignored when enable = '0'
clear : in std_logic; -- clear is ignored when enable = '1'

-- write side
wr_en : in std_logic;
din : in std_logic_vector(15 downto 0);

wr_rst_busy : out std_logic;
wr_data_count : out std_logic_vector(6 downto 0);
prog_full : out std_logic;
full : out std_logic;
overflow_sticky : out std_logic; -- use 'rst' or 'clear' to reset

-- read side
rd_en : in std_logic;
dout : out std_logic_vector(15 downto 0);

rd_rst_busy : out std_logic;
rd_data_count : out std_logic_vector(6 downto 0);
prog_empty : out std_logic;
empty : out std_logic;
underflow_sticky : out std_logic -- use 'rst' or 'clear' to reset
);
end rx_fifo;

architecture Behavioral of rx_fifo is

signal fifo_rst : std_logic;
signal fifo_wr_en : std_logic;

signal overflow : std_logic;
signal underflow : std_logic;

begin

...
-- xpm_fifo_sync: Synchronous FIFO -- Xilinx Parameterized Macro, Version 2017.2 xpm_fifo_sync_inst : xpm_fifo_sync generic map ( FIFO_MEMORY_TYPE => "auto", --string; "auto", "block", "distributed", or "ultra" ; ECC_MODE => "no_ecc", --string; "no_ecc" or "en_ecc"; FIFO_WRITE_DEPTH => 64, --positive integer WRITE_DATA_WIDTH => 16, --positive integer WR_DATA_COUNT_WIDTH => 7, --1 bit extra so counter cannot overflow. 2^7=128, while depth=64 PROG_FULL_THRESH => 54, --positive integer FULL_RESET_VALUE => 0, --positive integer; 0 or 1; READ_MODE => "fwft", --string; "std" or "fwft"; FIFO_READ_LATENCY => 0, --positive integer; (must be '0' with "fwft" mode) READ_DATA_WIDTH => 16, --positive integer RD_DATA_COUNT_WIDTH => 7, --1 bit extra so counter cannot overflow. 2^7=128, while depth=64 PROG_EMPTY_THRESH => 10, --positive integer DOUT_RESET_VALUE => "0", --string WAKEUP_TIME => 0 --positive integer; 0 or 2; ) port map ( rst => fifo_rst, wr_clk => clk, wr_en => fifo_wr_en, din => din, full => full, overflow => overflow, wr_rst_busy => wr_rst_busy, rd_en => rd_en, dout => dout, empty => empty, underflow => underflow, rd_rst_busy => rd_rst_busy, prog_full => prog_full, wr_data_count => wr_data_count, prog_empty => prog_empty, rd_data_count => rd_data_count, sleep => '0', injectsbiterr => '0', injectdbiterr => '0', sbiterr => open, dbiterr => open );

end Behavioral;

 

Then I packaged the IP, and added it to the block design of my top level project. Synthesis runs fine, but during implementation I get these errors :

 

[Project 1-486] Could not resolve non-primitive black box cell 'design_1_hdlc_ctrl_0_0_xpm_fifo_sync' instantiated as 'design_1_i/hdlc_ctrl_0/U0/rx_chan_i/rx_fifo_i/xpm_fifo_sync_inst' ["/home/zynqdev/Zynq/2017_2/hdlc_analyser/hdlc_analyser/hdlc_analyser.srcs/sources_1/bd/design_1/ipshared/5da6/src/rx_chan/rx_fifo.vhd":260]

 

Looks like Vivado does not pick up the XPM_FIFO_SYNC macro? I checked UG953, it states that for the IDE flow, the tools will parse the files added to the project and recognize the XPM's.

 

errors.png

 

I get a 2nd error during Opt Design, but.I guess that's a consequence of the first error :

 

[DRC INBB-3] Black Box Instances: Cell 'design_1_i/hdlc_ctrl_0/U0/rx_chan_i/rx_fifo_i/xpm_fifo_sync_inst' of type 'design_1_i/hdlc_ctrl_0/U0/rx_chan_i/rx_fifo_i/xpm_fifo_sync_inst/design_1_hdlc_ctrl_0_0_xpm_fifo_sync' has undefined contents and is considered a black box.  The contents of this cell must be defined for opt_design to complete successfully.

Any idea how to resolve this?

 

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6 Replies
Xilinx Employee
Xilinx Employee
1,859 Views
Registered: ‎08-01-2008

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

This issue is commonly seen in an IPI design.

It is caused by either of the following settings in the project being packaged as an IP:

 

  • Out-Of-Context.
    Ensure that there is no Out-Of-Context IP in the project before you package it.


  • Attributes Box Type in the RTL code. 
    Box Type settings will prevent Vivado from synthesizing the module in a packaged IP as the top level design will consider it as a black box. 
    As a result implementation will likely fail with a blackbox error or attached logic will be trimmed due to the missing component.

 

Thanks and Regards
Balkrishan
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Scholar ronnywebers
Scholar
1,856 Views
Registered: ‎10-10-2014

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

thanks @balkris

 

In the meantime I came accross the AR# 60834 you actually mention.

 

I think it's not the first option, as my IP consists purely of vhdl files, with that 1 file instantiationg an XPM_FIFO_SYNC (?). I have no other IP instantiated .

 

Initially I did have my package IP project set to out-of-context synthesis, and a xdc file with a clock definition, also with it's property set to out-of-context, to have some idea of timing performance. I did remove the 'mode out of context' from the synthesis settings,but that didn't change a thing. Also I don't think that ends up in the component.xml (?), at least I could not find a trace of it in the component.xml. But I do see the clocks_ooc.xdc file's property set to out of context in the component.xml -> could that xdc file and it's ooc property be a problem?

 

The 2nd option you mention 'Attributes Box Type in the RTL code', can you clarify that a bit more? Are these attributes that you add in the vhdl code? What kind of attributes could that be? I dont' think I used them, but it's interesting to know.

 

 

 

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Scholar ronnywebers
Scholar
1,843 Views
Registered: ‎10-10-2014

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

@balkris, I tried a reset of my block design's output products, and then used 'global synthesis' mode, as suggested in some posts. But that gives ta similar error :

 

[Project 1-486] Could not resolve non-primitive black box cell 'xpm_fifo_sync' instantiated as 'design_1_i/hdlc_ctrl_0/U0/rx_chan_i/rx_fifo_i/xpm_fifo_sync_inst' ["/home/zynqdev/Zynq/2017_2/hdlc_analyser/hdlc_analyser/hdlc_analyser.srcs/sources_1/bd/design_1/ipshared/5da6/src/rx_chan/rx_fifo.vhd":260]
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Scholar markcurry
Scholar
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Registered: ‎09-16-2009

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

Ronny,

 

Note - we don't use project mode, nor IPI, nor OOC in any form.

 

But, should you just be adding the following file to your build list:

$XILINX/data/ip/xpm/xpm_fifo/xpm_fifo.sv

 

The xpm_fifo_sync module is defined there (in plain, unencrypted, readable verilog).

 

Regards,

 

Mark

Scholar ronnywebers
Scholar
1,819 Views
Registered: ‎10-10-2014

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

I can give that a try @markcurry - thanks for the tip.

 

But stil it looks I did something wrong, or it might be a bug in Vivado, 'cause the xpm_sync_fifo works fine in my edit IP project where I do a detailed simulation.  But not when I integrate that custom IP in an application project. 

 

It looks kinda basic issue ... Vivado should infer / recognize the xpm_fifo_sync template I guess?

 

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Scholar ronnywebers
Scholar
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Registered: ‎10-10-2014

Re: XPM_FIFO_SYNC in custom IP : Could not resolve non-primitive black box cell

@balkris@markcurry - I solved my problem, but it looks like a Vivado bug to me :

 

I created a basic custom IP, containing only the XPM fifo with minimal connections. This IP was then added to an application project. The zip file containing both is attached.

 

When generating the bitstream of the application project, containing the custom IP, this gave a slightly different synthesis error (it's strange why this error is not the same as with my more complex IP, maybe because the XPM sits in the toplevel file (?). Note that 'fifo_test.vhd' is the custom IP top-level file that contains the XPM_FIFO_SYNC instantiation :

 

[Synth 8-4169] error in use clause: package 'vcomponents' not found in library 'xpm' [fifo_test.vhd:27]

'vcomponents' is a package in the xpm library.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Xilinx component used : XPM_FIFO_SYNC
Library xpm;
use xpm.vcomponents.all;
 
entity fifo_test is
...

Note that this part of the hdl code was copied from the XPM_FIFO_SYNC template in Vivado... → either the code template in Vivado is wrong, or this is a Vivado bug. Commenting out the xpm library also provokes some strange synthesis errors, so this xpm lib inclusion is definitely needed.

 

by googling I stumbled accross this : AR# 67815 - [Synth 8-4169] error in use clause: package 'vcomponents' not found in library 'xpm'

 

This AR proposes a tcl command as workaround :

set_property XPM_LIBRARIES {XPM_FIFO} [current_project]

As soons as I run this, the issue with the XPM_SYNC_FIFO was resolved!

 

or better - not immediately - I had to ged rid of the cached synthesis results, because the set_property command did not invalidate the cached IP ... see this post  (didn't get an answer to this post so far, so I just deleted all generated files from my project manually).

 

The AR also states that this is documented in the UG974 (Ultrascale Architecture Libraries Guide), but that is not the case - I did a search for 'XPM_LIRBRARIES' in UG974, but didn't find a single occurence. Chapter 2 page 4 states that vivado - when using the IDE - should automatically recognize XPMs. That is clearly not the case if the XPM is part of a custom IP (and I'm wondering if it is when the XPM is used in a project hdl file, didn't test that yet). The same goes for UG953 (7 series libraries guide). So the manuals are incomplete there.

 

I think Vivado should comply to it's documentation, and have all XPM_LIBRARIES enabled by default. To me this is a Vivado bug.

 

 

 

 

 

 

 

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