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Registered: ‎03-16-2010

XPS project: ngdbuild 455 - MIRQ line ends up with 2 drivers

I am trying to find out what causes this error:

ERROR:NgdBuild:455 - logical net 'plb_linux_Sl_MIRQ<40>' has multiple driver(s):
     pin G on block interconnect_0/XST_GND with type GND,
     pin G on block tft_bridge_0/XST_GND with type GND

Interconnect_0 is a custom peripheral which connects to 'plb_linux' and through a custom interconnect connects to an AXI bus. This bus is connected to a MIG generated memory controller. Without the DVI IP this works.


When we add the DVI IP 'xps_tft' it gets a PLB bus, a Xilinx PLB to AXI bridge and it is connected to the same AXI bus as the 'interconnect_0' component in order to access the memory.


We then get the error message during ngdbuild as posted above. In the system level and wrapper VHDL files from the 'hdl' folder it seems like plb_linux_Sl_MIRQ pin 40 is only assigned once so it seems like this is an issue happening inside the tools.


Is there something else I can look into?

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Xilinx Employee
Xilinx Employee
Registered: ‎06-14-2012

Re: XPS project: ngdbuild 455 - MIRQ line ends up with 2 drivers

These errors can occur when the netlists created are synthesized with the option to include I/O buffers. The default option for XST is "Add I/O buffers". If all of the I/O signals for this block already have IBUFs and OBUFs, when you try to include the block into the EDK design, PlatGen places additional I/O buffers. The errors will then occur because there are two sets of buffers (multiple drivers).  

To work around this issue, uncheck the option and resynthesize the design, as follows: 

1. Open your IP project in ISE. 
2. Right-click on Synthesize - XST. 
3. Select Properties. 
4. Select Xilinx Specific Options. 
5. Deselect Add I/O Buffers. 
6. Select OK. 
7. Resynthesize your design.

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