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Registered: ‎11-28-2011

Xilinx Vivado 2017.1 Constant block getting removed

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For some reason Constant blocks are getting optimized away in 2017.1. For Vivado 2015.4 I have the XAPP1082 which after PAR I can open up the routed.dcp file and verify that the 1G PCS/PMA core has the constants assigned to the configuration_vector[4:0] and configuration_valid.

 

But the same design (with the upgraded core 16.0), removes the Constant blocks and shows those inputs as "nc". 

 

 

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Explorer
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Registered: ‎04-05-2016

Re: Xilinx Vivado 2017.1 Constant block getting removed

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Have you confirmed that you need the configuration_vector[4:0] populated? Does the design work as expected? It is possible in the latest version of the core those inputs are no longer needed.

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Registered: ‎04-05-2016

Re: Xilinx Vivado 2017.1 Constant block getting removed

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Have you confirmed that you need the configuration_vector[4:0] populated? Does the design work as expected? It is possible in the latest version of the core those inputs are no longer needed.

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Registered: ‎11-28-2011

Re: Xilinx Vivado 2017.1 Constant block getting removed

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I'm thinking the latest version of the core, depending on how it's configured, doesn't need those vectors. What is also odd is that I put a constant on the AN vector as well and that gets removed. But we does use AN. In any case, we got both PCS/PMS cores to work now.
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Re: Xilinx Vivado 2017.1 Constant block getting removed

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Glad you got it working.

It's my understanding that some of the primatives that are displayed on the schematic are the result of macros that can be configured using generics and/or constants into their port statements. It is possible as the Vivado tools marched on, they found it more appropriate to use a generic to configure the block rather than constants on the inputs.
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