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Adventurer
Adventurer
9,868 Views
Registered: ‎12-01-2010

Xilinx design language (XDL) supported in Vivado?

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Hello all,

 

   I just checked Vivado to see if the XDL can still be used to make som very back-end modification to the circuit. I was actually making some logic modifations and clones relying on XDL. But it seems that vivado doesn't include the FPGA editor, which using ncd as the input. So I cannot get xdl from ncd file.

 

   Does't any one know if it is possible to make back-end changes to the post P/R circuit, like the LUT equation change?

 

   Thanks,

 

  Eric,

 

   

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Xilinx Employee
Xilinx Employee
16,809 Views
Registered: ‎09-20-2012

Re: Xilinx design language (XDL) supported in Vivado?

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Hi Eric,

 

I dont think there is a way to export readible PAR netlist.

 

You can use write_edif command to export the synthesized netlist but this will not have place and route info.

 

You can write some procedure in TCL to do these logic changes. For help on TCL scripting refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug894-vivado-tcl-scripting.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
9,864 Views
Registered: ‎07-21-2014

Re: Xilinx design language (XDL) supported in Vivado?

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Hi,

 

You can change LUT equation, select the LUT and set equation in property window.

 

Capture.PNG

 

Thanks,
Anusheel
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Thanks
Anusheel
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Xilinx Employee
Xilinx Employee
9,862 Views
Registered: ‎09-20-2012

Re: Xilinx design language (XDL) supported in Vivado?

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Hi,

 

To add,

 

NCD,XDL are not supported in Vivado.

 

Vivado device editor is equivalent to FPGA editor and you can make the logic changes.

 

Refer to page-129 "Logic changes" of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug904-vivado-implementation.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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Adventurer
Adventurer
9,843 Views
Registered: ‎12-01-2010

Re: Xilinx design language (XDL) supported in Vivado?

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Thanks for the prompt reply.

 

It looks nice to manually change single equatins. But my design requires to have the similar changes to a large nubmer of logic elements, including the logic copy, relocation and lut equation changes at post P&R stage. It is pretty convenient to do this in the readable XDL netlist using Java or python in my work.

 

  A further inqury,  is it possible to have this kind of bached process in Vivado? Or specifically, can I extract any readable post P/R netlist from Vivado?

 

  Regards,

  Eric,

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Moderator
Moderator
9,833 Views
Registered: ‎07-21-2014

Re: Xilinx design language (XDL) supported in Vivado?

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Hi,

 

You can write script to change large nubmer of logic elements.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Search related forums and make sure your query is not repeated.

 

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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Thanks
Anusheel
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Xilinx Employee
Xilinx Employee
16,810 Views
Registered: ‎09-20-2012

Re: Xilinx design language (XDL) supported in Vivado?

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Hi Eric,

 

I dont think there is a way to export readible PAR netlist.

 

You can use write_edif command to export the synthesized netlist but this will not have place and route info.

 

You can write some procedure in TCL to do these logic changes. For help on TCL scripting refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug894-vivado-tcl-scripting.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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