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Visitor
Visitor
415 Views
Registered: ‎03-16-2020

Xillinx Vhdl: could not get function return to output port

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Hi , im trying to use function to get the return value for output port but i get this error: 

ERROR:Pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Pack:18 - The design is too large for the given device and package.

function weight
			(x1,x2,x3 : integer)
			return integer is
	begin
		return x1 + 2*x2 + x3;

calc:process
		begin
			Eh := weight(pixel1,pixel2,pixel3);
			output <= Eh;
			
		end process;

 how to solve this?

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Scholar
Scholar
298 Views
Registered: ‎08-01-2012

The datasheet/userguide for your dev board will tell you the pinout for the FPGA device. These need to be assigned in your VIvado project.

For top level ports, I recommend you do not use integers.

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Scholar
Scholar
397 Views
Registered: ‎08-01-2012

This is unlikely to be a problem with the function. An integer is 32 bits. does "output" go to a pin? do you have 32 pins free to export all the bits?

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Visitor
Visitor
304 Views
Registered: ‎03-16-2020

Im not sure if its because integer, when i change 

output <= Eh;

to

output <= pixel1;

it fixed the error where pixel1 is integer too.

here is my entity

entity function_test is
    Port ( pixel1 : in  integer;
           pixel2 : in  integer;
           pixel3 : in  integer;
           output : out  integer);
end function_test;

anyway i just recently learning using vhdl how do you check available pins?

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Highlighted
Scholar
Scholar
299 Views
Registered: ‎08-01-2012

The datasheet/userguide for your dev board will tell you the pinout for the FPGA device. These need to be assigned in your VIvado project.

For top level ports, I recommend you do not use integers.

View solution in original post

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Visitor
Visitor
241 Views
Registered: ‎03-16-2020

thx for the solution it works. i change the return value from integer to 9 bit vector as well as the output type

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