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matthewhannon
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Registered: ‎12-25-2020

ZCU208 - Discrepancy between latest board schematics and user guide regarding UART voltages, pinouts, and constraints

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Hello,

I am trying to understand what are the correct package pins that I should connect my zynq_uart_ps_e_0_UART_1 interface to during the I/O port mapping (after synthesis). The latest user guide for the ZCU208 board (attached) on page 35 shows a different schematic for the USB UART JTAG hardware compared to the latest ZCU208 schematics (attached) which can be found on page 27. The schematic in the user guide shows a voltage of 1.8 volts while the official schematics show a voltage of 1.2 volts. Furthermore, the UART0_RXD_MIO19_TXD and UART0_TXD_MIO18_RXD are connected to different blocks than they are when compared to the latest ZCU208 user guide.

I think what I want is to connect my external UART interface to UART0_RXD_MIO19_TXD/UART0_TXD_MIO18_RXD and not UART2_TXD_FPGA_RXD/UART2_RXD_FPGA_TXD. Furthermore, if I try and connect the UART external interface to what I think are the correct ones (UART0_RXD_MIO19_TXD/UART0_TXD_MIO18_RXD) they go to package pins Y27 and W28 which according to the latest ZCU208 master XDC constraint file are not listed/activated by default. They are referred to as the following:

#Other net PACKAGE_PIN Y27 - UART0_TXD_MIO18_RXD Bank 500 - PS_MIO18
#Other net PACKAGE_PIN W28 - UART0_RXD_MIO19_TXD Bank 500 - PS_MIO19

compared to say the activated package pins such as:

set_property PACKAGE_PIN AT9 [get_ports "UART2_RXD_FPGA_TXD"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
set_property IOSTANDARD LVCMOS12 [get_ports "UART2_RXD_FPGA_TXD"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65

Essentially I am confused about regarding the latest user guide and the latest schematics (which show completely different hardware components with different voltages). Namely, which one I should believe and try to put into my Vivado design. Should I change the latest constraints file to activate package pins Y27 and W28 which are connected to bank 500 (which has a VCC1V8)?

Overall I don't know whether to believe the schematics in the latest ZCU208 user guide or actual latest schematics for the ZCU208 which show different hardware designs. Further adding to my confusion is the latest XDC constraints file which has Y27 and W28 commented out.

If anyone could please try to help me understand all of this I would greatly appreciate it.

Thank you for your time.

Sincerely,

-Matt

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shantmoses
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Registered: ‎07-01-2008

Matt,

I think the user guide schematic snippet is incorrect. I would trust the ZCU208 schematic more.

UART0 pins are connected to PS bank 500 and this bank is powered by 1.8V VCCO.

UART2 pins are connected to PL bank 65 next to PL_DDR4 interface pins and this bank is powered by 1.2V VCCO.

If you're planning on using the PS UART0 pins, they don't need to be included in the xdc file, you simply just need to enable the UART0 interface in the Zynq IP customization GUI.

 

Regards,

Shant

 

 

 

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shantmoses
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932 Views
Registered: ‎07-01-2008

Matt,

I think the user guide schematic snippet is incorrect. I would trust the ZCU208 schematic more.

UART0 pins are connected to PS bank 500 and this bank is powered by 1.8V VCCO.

UART2 pins are connected to PL bank 65 next to PL_DDR4 interface pins and this bank is powered by 1.2V VCCO.

If you're planning on using the PS UART0 pins, they don't need to be included in the xdc file, you simply just need to enable the UART0 interface in the Zynq IP customization GUI.

 

Regards,

Shant

 

 

 

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