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Visitor meakerb
Visitor
7,674 Views
Registered: ‎12-12-2011

Zynq FCLK to BUFGMUX without CLOCK_DEDICATED_ROUTE constraint

I am using Vivado 2015.3 and creating a design for the ZC702 board. I am trying to create a design that allows me to select either the FCLK0 from the processor system or the Si570 clock (brought in with a IBUFGDS) to be the clock for my logic.

 

I have a block design that routes FCLK0 out (as well as using it for clocking some AXI interfaces), and in the top level module I routed FCLK0 to the BUFGMUX. That didn't work, so I put a BUFG in the path (as suggested by UG949, in the section on cascaded clock buffers). That didn't work either.

 

I keep getting this type of error message

Implementation
Place Design
[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets BUFGMUX_inst_n_0] >

	BUFGMUX_inst (BUFGCTRL.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
	 BUFGCE_z_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y4
	 BUFGCE_y_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y3
	 BUFGCE_x_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y2
	 BUFGCE_w_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_gclkio_bufg
	Status: PASS 
	Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
	as the BUFG
	 diffbuf_inst (IBUFDS.O) is locked to IOB_X0Y26
	 BUFGMUX_inst (BUFGCTRL.I1) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

	Clock Rule: rule_cascaded_bufg
	Status: FAIL 
	Rule Description: Cascaded bufg (bufg->bufg) must be adjacent and cyclic
	 system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
	 BUFGMUX_inst (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
	ERROR: The above is also an illegal clock rule
	Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets system_i/processing_system7_0/inst/FCLK_CLK0] >

	Clock Rule: rule_ps7_bufg
	Status: PASS 
	Rule Description: A PS7 driving a BUFG must be placed on the same half side (top/bottom) of the device
	 system_i/processing_system7_0/inst/PS7_i (PS7.FCLKCLK[0]) is locked to PS7_X0Y0
	 and system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31


[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

 

So how do I configure this so that I don't have to use the set_property CLOCK_DEDICATED_ROUTE constriaint?

 

We are trying to evaluate the lower jitter Si570 and the effects it has on our system, so I would like to utilize the dedicated clock routing resources rather that the sub optimal routing through signal paths. Would using the set_property CLOCK_DEDICATED_ROUTE BACKBONE constraint (as opposed to the set_property CLOCK_DEDICATED_ROUTE FALSE constraint) force what I want?

 

Thanks

 

 

 

 

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2 Replies
Moderator
Moderator
7,673 Views
Registered: ‎07-01-2015

Re: Zynq FCLK to BUFGMUX without CLOCK_DEDICATED_ROUTE constraint

Hi @meakerb,

 

Please go through following Answer Record
http://www.xilinx.com/support/answers/54962.html

 

Also you can refer to the following thread that discusses similar issue.

https://forums.xilinx.com/t5/Implementation/Place-30-120-Sub-optimal-placement-for-a-BUFG-BUFG-cascade-pair/td-p/546781

 

Please let us know the outcomes.

 

Thanks,
Arpan

 

Thanks,
Arpan
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Historian
Historian
7,652 Views
Registered: ‎01-23-2009

Re: Zynq FCLK to BUFGMUX without CLOCK_DEDICATED_ROUTE constraint

I am not certain (since I would have to open the floorplan for this device to be sure), but it looks like you brought the external clock in on the CCIO on the lower half of the chip. The PS is in the upper half of the chip. Thus, the PS clock can only reach the upper 16 BUFGs and the external clock can only reach the lower 16 BUFGs. Hence they can't reach the same BUFGMUX.

 

Even putting the BUFG on one of them doesn't fix this, since the BUFG/BUFG cascades are all within the same half of the chip.

 

This being said, why don't you want to use the BACKBONE? This only matters if you need to preserve the phase of a clock. If the external clock doesn't clock any I/O, then its insertion delay is irrelevent, and there is no harm in using the BACKBONE for this clock.

 

Avrum

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