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Visitor zzmzc333
Visitor
1,677 Views
Registered: ‎01-27-2018

about the design comprised of Hard macros

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Hi!

 

If a design is made of Hard Macros, will the Hard Macros be optimized by ISE when I run design. And can those Hard Macros be edited by FPGA Editor?

 

Thank you very much! 

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Scholar jmcclusk
Scholar
2,366 Views
Registered: ‎02-24-2014

Re: about the design comprised of Hard macros

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Hard macros can actually also be created in RTL (Verilog & VHDL) by using attributes applied to cells and nets.   The flow is more complicated and somewhat more difficult in Verilog compared to VHDL.   It basically requires low level design, with primitive instantiation of the cells, then attaching location attributes to the cells.   This works both in ISE and Vivado.

Don't forget to close a thread when possible by accepting a post as a solution.
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Scholar jmcclusk
Scholar
1,597 Views
Registered: ‎02-24-2014

Re: about the design comprised of Hard macros

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Hard macros are untouched by ISE (synthesis, ngdbuild, place, etc).   The only way to modify them is using FPGA editor.

Don't forget to close a thread when possible by accepting a post as a solution.
Visitor zzmzc333
Visitor
1,574 Views
Registered: ‎01-27-2018

Re: about the design comprised of Hard macros

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Thank you for your help!

I have tried to edit hard macro in FPGA editor. I opened a design in FPGA editor and then "Add Hard Macro Instance" to add the hard macro which I have already prepared. Then I go inside the hard macro slice, it does not allow me to do modification and gives me a message:

WARNING:FPGAEditor:101 - The component "HM/CNT_2" is part of a hard macro
You must edit the hard macro definition itself.

Is this not a correct way to call a hard macro? Thank you.

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Scholar jmcclusk
Scholar
1,567 Views
Registered: ‎02-24-2014

Re: about the design comprised of Hard macros

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Try these instructions in AR#10901 for creating/editing hard macros.

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Visitor zzmzc333
Visitor
1,563 Views
Registered: ‎01-27-2018

Re: about the design comprised of Hard macros

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Thank you. I have tried this and this how I made the Hard Macro which I added in the design. I think I am confused about one thing: I have seen someone instantiates hard macro in verilog code and Xilinx also provides a way to add hard macro in FPGA editor, I am confused if in both two ways, the hard macros included in a design can be edited in FPGA editor? I appreciate your help and it helped a lot.  

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Scholar jmcclusk
Scholar
2,367 Views
Registered: ‎02-24-2014

Re: about the design comprised of Hard macros

Jump to solution

Hard macros can actually also be created in RTL (Verilog & VHDL) by using attributes applied to cells and nets.   The flow is more complicated and somewhat more difficult in Verilog compared to VHDL.   It basically requires low level design, with primitive instantiation of the cells, then attaching location attributes to the cells.   This works both in ISE and Vivado.

Don't forget to close a thread when possible by accepting a post as a solution.
Visitor zzmzc333
Visitor
1,553 Views
Registered: ‎01-27-2018

Re: about the design comprised of Hard macros

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Thanks a lot for your help. I already have a hard macro and I will try if I can instantiate it in verilog.

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