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Adventurer
Adventurer
943 Views
Registered: ‎05-18-2017

about the implementation duplication in virtex7

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Hi, there

 

Now, I am working virtex-7-2000T. Basically, there are 4 NAND PHY, which support DDR interface. So, the timing requirement is a little bit tight. So, after we setup the correct constrains in the XDC, the timing is closed on 0326 implementation. But, on 0328, we change the RTL, not NAND PHY design, VIVADO report timing failure, around -3ns. But, 0326 and 0328 have exact same design for NAND PHY. The following is the 4 sub-module with DDR interface. 

 

u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[0].u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho

u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[1].u_ndphy_ch_top_inst.u_ndphy_ch_top

u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[2].u_ndphy_ch_top_inst.u_ndphy_ch_top

u_core_top/u_pd_top/u_ncb_top/ndphy_ch_inst[3].u_ndphy_ch_top_inst_ho.u_ndphy_ch_top_ho

 

I am thinking whether there is any way for me to copy the 0326 NAND_PHY to 0328 design directly, including loc, FF, route path, etc.  I try floorplan before, but timing is worse. I hope that we can get the consistent implementation when NAND PHY is exactly same. 

 

It is highly appreciated it if someone can solve my problem. thanks

 

Ping Chen

 

2018.3.29

 

 

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
1,179 Views
Registered: ‎05-08-2012

Re: about the implementation duplication in virtex7

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Hi @chenpingx. There are two reuse flows that I can suggest that might help. The first is the incremental compile flow. This is more useful with designs smaller changes between design iterations. With this flow, a previous reference checkpoint will be used by the implementation tools to complete the placement and routing of the new version. The Implementation Guide has more on this on page 94:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug904-vivado-implementation.pdf

 

There is also Hierarchical Design flows. There are several levels of reuse, but you could physically separate areas that you want to keep the same placement and routing. You might not see the same QOR though, as the physical separation will limit the placement and routing options. The below Hierarchical Design Guide has more information.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf

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5 Replies
Xilinx Employee
Xilinx Employee
1,180 Views
Registered: ‎05-08-2012

Re: about the implementation duplication in virtex7

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Hi @chenpingx. There are two reuse flows that I can suggest that might help. The first is the incremental compile flow. This is more useful with designs smaller changes between design iterations. With this flow, a previous reference checkpoint will be used by the implementation tools to complete the placement and routing of the new version. The Implementation Guide has more on this on page 94:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug904-vivado-implementation.pdf

 

There is also Hierarchical Design flows. There are several levels of reuse, but you could physically separate areas that you want to keep the same placement and routing. You might not see the same QOR though, as the physical separation will limit the placement and routing options. The below Hierarchical Design Guide has more information.

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug905-vivado-hierarchical-design.pdf

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Adventurer
Adventurer
850 Views
Registered: ‎05-18-2017

Re: about the implementation duplication in virtex7

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thanks for reply. I will try #2 for hierarchy design. 

 

For incremental compile, I tried it before, even worse.

 

Ping Chen

 

2018.4.6

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Moderator
Moderator
814 Views
Registered: ‎01-16-2013

Re: about the implementation duplication in virtex7

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@chenpingx,

 

Did you try the HD flow? 

Also if you can share the design which is showing bad results with incremental compilation flow then I can forward it to Factory.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Adventurer
Adventurer
808 Views
Registered: ‎05-18-2017

Re: about the implementation duplication in virtex7

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thanks for your information. 

 

update the status. After applying the LOC constrains the IDDR/ODDR, it is quite consistent to get the good implementation result, just -0.2 ns setup timing violation. So, i think it is OK now. 

 

For HD, i don't try it. 

 

Ping Chen

 

2018.4.10

 

 

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Moderator
Moderator
738 Views
Registered: ‎01-16-2013

Re: about the implementation duplication in virtex7

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@chenpingx,

 

Thanks for the update. For closing on timing, i would request you to post the new query in timing board.

Please close this thread by marking the above post of @marcb as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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