07-02-2019 03:50 AM - edited 07-02-2019 04:13 AM
I have aurora 8b10b example. TXP ,TXN, RXP, RXN are the output and input ports repectively. Below is the
ports of top level module.
entity aurora_8b10b_v6_2_example_design is
USE_CHIPSCOPE : integer := 1;
SIM_GTXRESET_SPEEDUP : integer := 1 --Set to 1 to speed up sim reset
-- User I/O
RESET : in std_logic;
HARD_ERR : out std_logic;
SOFT_ERR : out std_logic;
FRAME_ERR : out std_logic;
ERR_COUNT : out std_logic_vector(0 to 7);
LANE_UP : out std_logic;
CHANNEL_UP : out std_logic;
INIT_CLK_P : in std_logic;
INIT_CLK_N : in std_logic;
GT_RESET_IN : in std_logic;
GTXQ0_P : in std_logic;
GTXQ0_N : in std_logic;
-- GT I/O
RXP : in std_logic;
RXN : in std_logic;
TXP : out std_logic;
TXN : out std_logic
TXP,TXN, RXN,RXP were not present in the IP created UCF file. So, I put them in the ucf like this
NET RXP LOC=D5;
NET RXN LOC=D6;
NET TXP LOC=B1;
NET TXN LOC=B2;
BUT, I got this error during mapping.
ERROR:Place:1073 - Placer was unable to create RPM[GTXE_RPMs] for the component
aurora_module_i/gtx_wrapper_i/GTXE1_INST/gtxe1_i of type GTXE for the
The reason for this issue:
All of the logic associated with this structure is locked and the relative
placement of the logic violates the structure. The problem was found between
the relative placement of GTXE
aurora_module_i/gtx_wrapper_i/GTXE1_INST/gtxe1_i at site GTXE1_X0Y1 and IPAD
RXN at site IPAD_X1Y108. The following components are part of this
07-02-2019 10:14 AM - edited 07-02-2019 10:15 AM
Hi, @amit_kumar ,
You can loc the GT by setting the location of gtxe1 or setting the location of TXP/TXN/RXP/RXN port.
If you set both of them, the location should be compatible.
If you intend to loc the TXP/TXN/RXP/RXN port, you need to remove the loc constraint of gtxe1.
PS: What's the device package of your design?