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Participant
Participant
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Registered: ‎02-01-2008

avoid using of DSP blocks in FIR COMPILER 7.2

Hello,

I have to implement FIR filters with constant coefficients. I am using the FIR compiler 7.2.  Because coefficients are constants I would like to avoid the using of DSP blocks. In synthesis parameters, I force the maximum number of DSP equal to 0. 

However, after the implementation, the resources utilization report told me that  DSP BLOCKS have been used.

Is it possible to force the ip core generator to not use DSP-blocks?

 

Luca

 

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Xilinx Employee
Xilinx Employee
532 Views
Registered: ‎05-22-2018

Re: avoid using of DSP blocks in FIR COMPILER 7.2

Hi @svip,

 

I am not sure for the IP core, but generally we can \restrict absorption of Registers into DSP blocks using the KEEP attribute.

For more information please check page no.60 of thr following UG901 link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf

 

Thanks,

Raj

 

 

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Moderator
Moderator
506 Views
Registered: ‎01-16-2013

Re: avoid using of DSP blocks in FIR COMPILER 7.2

@svip

 

If the DSP blocks are coming from IP in instantiated form then it cannot be avoided. 

 

--Syed

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