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Explorer
Explorer
784 Views
Registered: ‎04-11-2016

clock planning option in ultrascale

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Hi,

I generated open example design for pcie gen3 for xcku035 kintex ultrascale. I wonder while opening implemented design why clock planning option doesn't appear to see transceivers configuration in vivado 16.3. along with i/o planning , floor planning.

Is there any way to open this? may be from TCL command?

 

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1 Solution

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Xilinx Employee
Xilinx Employee
973 Views
Registered: ‎05-08-2012

Re: clock planning option in ultrascale

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Hi @fpgalearner. Thanks for the clarification. That is correct. The Clock Planning Layout will only be seen for 7-Series designs. For UltraScale designs. the report_clock_utilization command is helpful for identifying how many clock resources have been constrained, and gives additional information.

 


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Xilinx Employee
Xilinx Employee
755 Views
Registered: ‎05-08-2012

Re: clock planning option in ultrascale

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Hi @fpgalearner. Is there more details, or an image to help identify what is missing in Vivado? Are design objects (cells/ports) related to Transceivers missing. Is a certain Vivado IDE view not present?

 

It sounds like you might be looking for the IO Planning Layout. This can be selected from the Layout Selector at the top of the IDE. Page 20 of the Vivado IDE Guide has more on this:

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug893-vivado-ide.pdf

 

 

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Explorer
Explorer
750 Views
Registered: ‎04-11-2016

Re: clock planning option in ultrascale

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Hi @marcb in same 20 page in Vivado IDE you mentioned , there is also clock planning option in dropdown menu. Which does not appear in my case in vivado IDE for ultra scale case design.

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Xilinx Employee
Xilinx Employee
974 Views
Registered: ‎05-08-2012

Re: clock planning option in ultrascale

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Hi @fpgalearner. Thanks for the clarification. That is correct. The Clock Planning Layout will only be seen for 7-Series designs. For UltraScale designs. the report_clock_utilization command is helpful for identifying how many clock resources have been constrained, and gives additional information.

 


*Please mark replies with the "Accept as solution" option if they are found to be helpful

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Moderator
Moderator
646 Views
Registered: ‎01-16-2013

Re: clock planning option in ultrascale

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@fpgalearner,

 

If your query is addressed, can you please close this thread by marking the post which answered your query as "Accept as Solution"

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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