04-15-2021 07:03 AM
Hello, I'm currently trying to use an "vivado EDIF flow". using an edif file generated by synplify_pro, in which I have a black box for my clock generator.
Generally I use Clocking wizard (6.0) into RTL project to generate adequate clock module.
How can I replace my black box by an allready generated clk_wiz?
a this time, implementation of my edif failed because he find a black box ( [DRC INBB-3] Black Box Instances: Cell 'clk0' of type 'clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.)
Hope you understand my issue, I'm sure it is possible to import existing clock block but I didn't find the way!
04-15-2021 09:52 PM