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balcells
Visitor
Visitor
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Registered: ‎01-23-2018

clocking wizard and EDIF Flow

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Hello, I'm currently trying to use an "vivado EDIF flow". using an edif file generated by synplify_pro, in which I have a black box for my clock generator. 

Generally I use Clocking wizard (6.0) into RTL project to generate adequate clock module.

How can I replace my black box by an allready generated clk_wiz?

a this time, implementation of my edif failed because he find a black box ( [DRC INBB-3] Black Box Instances: Cell 'clk0' of type 'clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.)

Hope you understand my issue, I'm sure it is possible to import existing clock block but I didn't find the way!

Regards

André  

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balcells
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Registered: ‎01-23-2018

it is OK now. thank you

View solution in original post

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chinmays
Xilinx Employee
Xilinx Employee
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Registered: ‎06-27-2018

Hi @balcells,

Have a look at following chapter in UG896-chapter 5 (click on hyperlink). Create a RTL project in vivado > create a wrapper around the edif file > add the IP xci file in the project.  

~Chinmay

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balcells
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Registered: ‎01-23-2018

it is OK now. thank you

View solution in original post

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