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Visitor asarmiento
Visitor
2,112 Views
Registered: ‎11-17-2017

combinational loop

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Hello, 

 

I am doing a ring oscilator with luts, everything is fine but when I try to generate the bitstream vivado get me a error. I readed in other post that inserting the next code I could generate the file.

 

set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets salida_0]

set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]

 

I do not achieve that the error change to warning.

 

[DRC LUTLP-1] Combinatorial Loop Alert: 1026 LUT cells form a 
combinatorial loop. This can create a race condition. Timing analysis may not be accurate.
The preferred resolution is to modify the design to remove combinatorial logic loops. If the
loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting
the following XDC constraint on any one of the nets in the loop:
'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is
salida_0. Please evaluate your design. The cells in the loop are: cantidad_slices[0].primero.l2, cantidad_slices[1].condicion.slice[1].lutero, cantidad_slices[1].condicion.slice[2].lutero,
cantidad_slices[1].condicion.slice[3].lutero, cantidad_slices[1].condicion.slice[4].lutero, cantidad_slices[2].condicion.slice[1].lutero, cantidad_slices[2].condicion.slice[2].lutero,
cantidad_slices[2].condicion.slice[3].lutero, cantidad_slices[2].condicion.slice[4].lutero, cantidad_slices[3].condicion.slice[1].lutero, cantidad_slices[3].condicion.slice[2].lutero,
cantidad_slices[3].condicion.slice[3].lutero, cantidad_slices[3].condicion.slice[4].lutero, cantidad_slices[4].condicion.slice[1].lutero, cantidad_slices[4].condicion.slice[2].lutero...
and (the first 15 of 1026 listed).
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1 Solution

Accepted Solutions
Moderator
Moderator
2,906 Views
Registered: ‎02-07-2008

Re: combinational loop

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Hi @asarmiento, how are you setting the various set_property constraints? Try putting them in a Tcl file, adding the Tcl file to the project.

 

I just tried setting "set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]" on a test case and it worked for me. Initially, I opened the route_design DCP and, in the Tcl Console, ran "write_bitstream -force <name_of_bitfile>.bit", resulting in a DRC Errors:

 

ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is design_1_i/heater_and_decode_0/inst/heater/hsub[0].HEAT_MIDDLE/hsub[0].HEAT_CORE/LUT_0/O5. Please evaluate your design. The cells in the loop are: design_1_i/heater_and_decode_0/inst/heater/hsub[0].HEAT_MIDDLE/hsub[0].HEAT_CORE/LUT_0/LUT5.

Then, in the Tcl Console, set:

set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]

 

re-ran "write_bitstream -force <name_of_bitfile>.bit", resulting in the bitstream successfully generated:

 

Writing bitstream ./bit.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully

 

If this doesn't work, are you able to submit the project? If necessary, I can contact you offline for this.

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5 Replies
Moderator
Moderator
2,101 Views
Registered: ‎02-07-2008

Re: combinational loop

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Hi @asarmiento, try: set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]

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Don’t forget to reply, kudo, and accept as solution.
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Scholar austin
Scholar
2,097 Views
Registered: ‎02-27-2008

Re: combinational loop

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Another suggestion,

 

Place an 2 input AND gate in your ring, use the 2nd input as a 'ring enable.'  Presenting that enable to an IO pin that has a switch on it allows you to turn the ring on and off so it breaks the loop if you desire (turn off the ring).  Not intended to prevent the error (critical warning warning) but useful...and sometimes does 'fool' the tool to not throw errors.

Austin Lesea
Principal Engineer
Xilinx San Jose
Highlighted
Visitor asarmiento
Visitor
2,059 Views
Registered: ‎11-17-2017

Re: combinational loop

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Thank you, 

 

I tried : set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]
But the result is the same error. Also I tried with a gate XOR in the entry of the ring oscilator and again the same result.

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Moderator
Moderator
2,907 Views
Registered: ‎02-07-2008

Re: combinational loop

Jump to solution

Hi @asarmiento, how are you setting the various set_property constraints? Try putting them in a Tcl file, adding the Tcl file to the project.

 

I just tried setting "set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]" on a test case and it worked for me. Initially, I opened the route_design DCP and, in the Tcl Console, ran "write_bitstream -force <name_of_bitfile>.bit", resulting in a DRC Errors:

 

ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is design_1_i/heater_and_decode_0/inst/heater/hsub[0].HEAT_MIDDLE/hsub[0].HEAT_CORE/LUT_0/O5. Please evaluate your design. The cells in the loop are: design_1_i/heater_and_decode_0/inst/heater/hsub[0].HEAT_MIDDLE/hsub[0].HEAT_CORE/LUT_0/LUT5.

Then, in the Tcl Console, set:

set_property IS_ENABLED FALSE [get_drc_checks LUTLP-1]

 

re-ran "write_bitstream -force <name_of_bitfile>.bit", resulting in the bitstream successfully generated:

 

Writing bitstream ./bit.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 302 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully

 

If this doesn't work, are you able to submit the project? If necessary, I can contact you offline for this.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor asarmiento
Visitor
2,034 Views
Registered: ‎11-17-2017

Re: combinational loop

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hi @peadard thank you very much for the advice. It works, I went able to program my board with the bitstream generated.  I have more problems with the design, Can I send you the code and you tell me what do you think about it?

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