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rex_nyu
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Registered: ‎08-12-2011

constraint error and illegal load problem

Hi all,

 

I am trying to test a very simple deskew circuit on a virtex-2 FPGA. I use the deskew IP provided by Xilinx. I also try to observe the related signals on GPIO pins. But I have got the following translate error in my design. The details of the error and the design is pasted below. Please give me some help.

 

 

Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <INST "rex_clk"  LOC="N3" |>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD="LVCMOS33" ;>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Done...
Checking Partitions ...

Checking expanded design ...
ERROR:NgdBuild:809 - output pad net 'clk_o' has an illegal load:
     pin C on block cnt_0 with type FDC


 

 

 

 

Verilog module

------------------------------------------------------------

module xc2vp30(
    //probing
    output rex_clk,
    output rex_rst,
    output rex_cnt_i,
    output rex_cnt_o,
    
    input rst,
    input clk,
    output clk_o,
    output rst_o,

    input cnt_i,
    output cnt_o
);

wire clk_ddr;
reg cnt;

assign rex_clk = clk_ddr;
assign rex_rst = rst;
assign rex_cnt_o = cnt;
assign rex_cnt_i = cnt_i;

assign clk_o = clk_ddr;
assign rst_o = rst;
assign cnt_o = cnt;


always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt <= 1'b0;
    else
        cnt <= cnt + 1'b1;
end

////////////////////Deskew/////////////////////

deskew deskew_0(
    .U1_CE_IN(1'b0),
        .U1_CLKFB_IN(clk_ddr),
        .U1_CLKIN_IN(clk),
        .U1_CLR_IN(rst),    //high reset
        .U1_PRE_IN(1'b0),
        .U1_RST_IN(rst),    //high reset
        .U2_RST_IN(rst),
        .DDR_CLK0_OUT(clk_ddr),
        .U1_CLKIN_IBUFG_OUT(),
        .U1_CLK0_OUT(),
        .U1_CLK180_OUT(),
        .U1_LOCKED_OUT(),
        .U2_CLK0_OUT(),
        .U2_LOCKED_OUT()
);
endmodule
--------------------------------------------------------------

 

UCF file

--------------------------------------------------------------

#########################################################
NET "clk" PERIOD = 40 ns HIGH 50%;
NET "clk" TNM_NET = clk;
#================================================ Pin assignment
#------------------------------------------------ Clock, reset, LED, and SW.
INST "clk"          LOC="B13" | IOSTANDARD="LVCMOS33";           # Clock input (X2)
INST "rst"             LOC="E21" | IOSTANDARD="LVCMOS33";           # Reset input

INST "clk_o"       LOC="AE1" | IOSTANDARD="LVCMOS33";              # Clock output
INST "rst_o"          LOC="Y26" | IOSTANDARD="LVCMOS33";               # Reset output
INST "cnt_o"          LOC="U2" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data output
INST "cnt_i"          LOC="V5" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data input

INST "rex_clk"     LOC="N3" | IOSTANDARD="LVCMOS33" ;           #  observe clk output
INST "rex_rst"     LOC="M4" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe Reset output

INST "rex_cnt_i"     LOC="L3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe
INST "rex_cnt_o"     LOC="K3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe

--------------------------------------------------------------

 

 

 

 

 

 

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rex_nyu
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Registered: ‎08-12-2011

Forgot to mention, I am using ISE 10.1 and the FPGA is xc2vp30-fg676-5.

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gszakacs
Professor
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Registered: ‎08-14-2007

The error message implies that rex_clk was removed from the design.  You may want to

check the synthesis report to see if there are some warnings that relate to this signal.  Check

to make sure that your deskew module's DDR_CLK0_OUT port is being driven.

 

One other possibility is that the assignment:

 

assign rex_clk = clk_ddr;

 

has caused the signal rex_clk to be re-named in the netlist generated by ISE.  I have seen

this in some cases, but not on top level module ports.  Then translate will not find rex_clk,

but will have some other name, possibly clk_ddr.

 

Finally, the real way to bring a clock signal to a pin is to use a DDR output flop.  In Virtex 2,

it is possible to route a clock signal to a pin directly, but the routing requires the use of a

special switchbox only located on the top or bottom of the die.  This means that depending

on the pin location,you could have several nanoseconds of routing delay between the global

clock net and the IO buffer.

 

-- Gabor

-- Gabor